CD4724BCMX

CD4724BCMX Datasheet

CD4724BC 8-Bit Addressable Latch

Part	Datasheet
CD4724BCMX	CD4724BCMX (pdf)

Related Parts	Information
CD4724BCM	CD4724BCM
CD4724BCN	CD4724BCN

PDF Datasheet Preview
CD4724BC 8-Bit Addressable Latch CD4724BC 8-Bit Addressable Latch The CD4724BC is an 8-bit addressable latch with three address inputs an active low enable input E , active high clear input CL , a data input D and eight outputs Data is entered into a particular bit in the latch when that is addressed by the address inputs and the enable E is LOW. Data entry is inhibited when enable E is HIGH. When clear CL and enable E are HIGH, all outputs are LOW. When clear CL is HIGH and enable E is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode E = CL = LOW , changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode E = HIGH, CL = LOW . s Wide supply voltage range 3.0V to 15V s High noise immunity VDD typ. s Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS s Serial to parallel capability s Storage register capability s Random addressable data entry s Active high demultiplexing capability s Common active high clear Ordering Code: Order Number Package Number Package Description CD4724BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4724BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Mode Selection E CL Addressed Unaddressed Mode Latch Latch L Follows Data Holds Previous Addressable Data Latch H L Hold Previous Holds Previous Memory Data Data L H Follows Data Reset to “0” Demultiplexer H Reset to “0” Reset to “0” Clear Top View 2002 Fairchild Semiconductor Corporation DS006003 CD4724BC Logic Diagram CD4724BC Absolute Maximum Ratings Note 1 Note 2 DC Supply Voltage VDD Input Voltage VIN Storage Temperature TS Power Dissipation PD Dual-In-Line Small Outline Lead Temperature TL Soldering, 10 seconds −0.5V to +18 VDC −0.5V to VDD VDC −65°C to +150°C 700 mW 500 mW 260°C Recommended Operating Conditions Note 2 DC Supply Voltage VDD 3.0V to 15 VDC Input Voltage VIN 0V to VDD VDC Operating Temperature Range TA −55°C to +125°C Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and Electrical Characteristics” provide conditions for actual device operation.

PDF Datasheet Preview

CD4724BC 8-Bit Addressable Latch

CD4724BC 8-Bit Addressable Latch

The CD4724BC is an 8-bit addressable latch with three address inputs an active low enable input E , active high clear input CL , a data input D and eight outputs

Data is entered into a particular bit in the latch when that is addressed by the address inputs and the enable E is LOW. Data entry is inhibited when enable E is HIGH.

When clear CL and enable E are HIGH, all outputs are LOW. When clear CL is HIGH and enable E is LOW, the channel demultiplexing occurs. The bit that is addressed has an active output which follows the data input while all unaddressed bits are held LOW. When operating in the addressable latch mode E = CL = LOW , changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode E = HIGH, CL = LOW .
s Wide supply voltage range 3.0V to 15V s High noise immunity VDD typ. s Low power TTL compatibility:
fan out of 2 driving 74L or 1 driving 74LS s Serial to parallel capability s Storage register capability s Random addressable data entry s Active high demultiplexing capability s Common active high clear
Ordering Code:

Order Number Package Number

Package Description

CD4724BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4724BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Truth Table

Mode Selection

E CL Addressed Unaddressed

Mode

Latch

Latch

L Follows Data Holds Previous Addressable

Data

Latch

H L Hold Previous Holds Previous Memory

Data

Data

L H Follows Data Reset to “0”

Demultiplexer

H Reset to “0” Reset to “0”

Clear

Top View
2002 Fairchild Semiconductor Corporation DS006003

CD4724BC

Logic Diagram

CD4724BC

Absolute Maximum Ratings Note 1

Note 2

DC Supply Voltage VDD Input Voltage VIN Storage Temperature TS Power Dissipation PD

Dual-In-Line

Small Outline

Lead Temperature TL Soldering, 10 seconds
−0.5V to +18 VDC −0.5V to VDD VDC
−65°C to +150°C
700 mW 500 mW
260°C

Recommended Operating Conditions Note 2

DC Supply Voltage VDD
3.0V to 15 VDC

Input Voltage VIN
0V to VDD VDC

Operating Temperature Range TA
−55°C to +125°C

Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and Electrical Characteristics” provide conditions for actual device operation.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CD4724BCMX Datasheet file may be downloaded here without warranties.

Datasheet ID: CD4724BCMX 513588