74LVT16245MEAX

74LVT16245MEAX Datasheet

74LVT16245<br>• 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs

Part	Datasheet
74LVT16245MEAX	74LVT16245MEAX (pdf)

Related Parts	Information
74LVTH16245MTD	74LVTH16245MTD
74LVTH16245MEA	74LVTH16245MEA
74LVT16245MEA	74LVT16245MEA
74LVTH16245MTDX	74LVTH16245MTDX
74LVTH16245MEAX	74LVTH16245MEAX
74LVT16245MTD	74LVT16245MTD
74LVT16245MTDX	74LVT16245MTDX

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74LVT16245 • 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs 74LVT16245 • 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVTH16245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16245 and LVTH16245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH16245 , also available without bushold feature 74LVT16245 . s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink mA s Functionally compatible with the 74 series 16245 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model !2000V Machine model !200V Charged-device !1000V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary Ordering Code: Order Number Package Number Package Description 74LVT16245GX Note 1 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Preliminary [Tape and Reel] 74LVT16245MEA Note 2 MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74LVT16245MTD Note 2 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide 74LVTH16245GX Note 1 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Preliminary [Tape and Reel] 74LVTH16245MEA Note 2 MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74LVTH16245MTD Note 2 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 1 BGA package available in Tape and Reel only. Note 2 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol 2005 Fairchild Semiconductor Corporation DS500152 74LVT16245 • 74LVTH16245 Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Names OEn T/Rn NC Output Enable Input Active LOW Transmit/Receive Input Side A Inputs/3-STATE Outputs Side B Inputs/3-STATE Outputs No Connect FBGA Pin Assignments NC T/R1 OE1 NC B1 NC A1 B3 VCC A3 B5 GND A5 B7 GND A7 B9 GND A9 B12 B11 VCC A11 A12 B14 B13 NC A13 A14 B15 NC T/R2 OE2 NC A15 Truth Tables Inputs T/R1 Outputs Bus Data to Bus Data to Bus State on Inputs T/R2 H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Outputs Bus Data to Bus Data to Bus State on 74LVT16245 • 74LVTH16245 Functional Description The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Logic Diagrams Note Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVT16245 • 74LVTH16245 Absolute Maximum Ratings Note 3 VCC VI VO Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current

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74LVT16245
• 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs
74LVT16245
• 74LVTH16245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs

The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state.

The LVTH16245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These non-inverting transceivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16245 and LVTH16245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH16245 , also available without bushold feature 74LVT16245 .
s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Outputs source/sink mA s Functionally compatible with the 74 series 16245 s Latch-up performance exceeds 500 mA s ESD performance:

Human-body model !2000V Machine model !200V Charged-device !1000V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary
Ordering Code:

Order Number

Package Number

Package Description
74LVT16245GX Note 1

BGA54A
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide

Preliminary [Tape and Reel]
74LVT16245MEA Note 2

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74LVT16245MTD Note 2

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
74LVTH16245GX Note 1

BGA54A
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide

Preliminary [Tape and Reel]
74LVTH16245MEA Note 2

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74LVTH16245MTD Note 2

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide

Note 1 BGA package available in Tape and Reel only.
Note 2 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol
2005 Fairchild Semiconductor Corporation DS500152
74LVT16245
• 74LVTH16245

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FBGA Top Thru View

Pin Descriptions

Pin Names

OEn T/Rn NC

Output Enable Input Active LOW Transmit/Receive Input Side A Inputs/3-STATE Outputs Side B Inputs/3-STATE Outputs No Connect

FBGA Pin Assignments

NC T/R1 OE1 NC

B1 NC A1

B3 VCC A3

B5 GND A5

B7 GND A7

B9 GND A9

B12 B11 VCC A11 A12

B14 B13 NC A13 A14

B15 NC T/R2 OE2 NC A15

Truth Tables

Inputs

T/R1

Outputs

Bus Data to Bus Data to Bus State on

Inputs

T/R2

H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance

Outputs

Bus Data to Bus Data to Bus State on
74LVT16245
• 74LVTH16245

Functional Description

The LVT16245 and LVTH16245 contain sixteen non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.

Logic Diagrams

Note Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVT16245
• 74LVTH16245

Absolute Maximum Ratings Note 3

VCC VI VO

Parameter Supply Voltage DC Input Voltage Output Voltage

DC Input Diode Current

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Datasheet ID: 74LVT16245MEAX 513430