CD4019BCN

CD4019BCN Datasheet

CD4019BC Quad AND-OR Select Gate

Part	Datasheet
CD4019BCN	CD4019BCN (pdf)

PDF Datasheet Preview
CD4019BC Quad AND-OR Select Gate CD4019BC Quad AND-OR Select Gate The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These complementary MOS CMOS transistors provide the building blocks for the 4 “AND-OR select” gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits KA and KB. All inputs are protected against static discharge damage. s Wide supply voltage range 3.0V to 15V s High noise immunity VDD typ. s Low power TTL compatibility Fan out of 2 driving 74L or 1 driving 74LS • AND-OR select gating • Shift-right/shift-left registers • True/complement selection • AND/OR/EXCLUSIVE-OR selection Ordering Code: Order Number Package Number Package Description CD4019BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD4019BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View 2002 Fairchild Semiconductor Corporation DS005952 CD4019BC Schematic Diagram Schematic diagram for 1 of 4 identical stages CD4019BC Absolute Maximum Ratings Note 1 Note 2 Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD Dual-In-Line Small Outline Lead Temperature TL Soldering, 10 seconds −0.5V to +18V −0.5V to VDD +0.5V −65°C to +150°C 700 mW 500 mW 260°C Recommended Operation Conditions Note 2 DC Supply Voltage VDD +3V to +15V Input Voltage VIN 0V to VDDV Operating Temperature Range TA −55°C to +125°C Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Note 2 VSS = 0V unless otherwise specified. DC Electrical Characteristics Note 3 Parameter Conditions Quiescent Device VDD = 5V Current VDD = 10V VDD = 15V LOW Level \|IO\| < 1 µA Output Voltage VDD = 5V VDD = 10V VDD = 15V

PDF Datasheet Preview

CD4019BC Quad AND-OR Select Gate

CD4019BC Quad AND-OR Select Gate

The CD4019BC is a complementary MOS quad AND-OR select gate. Low power and high noise margin over a wide voltage range is possible through implementation of N- and P-channel enhancement mode transistors. These complementary MOS CMOS transistors provide the building blocks for the 4 “AND-OR select” gate configurations, each consisting of two 2-input AND gates driving a single 2-input OR gate. Selection is accomplished by control bits KA and KB. All inputs are protected against static discharge damage.
s Wide supply voltage range 3.0V to 15V s High noise immunity VDD typ. s Low power TTL compatibility Fan out of 2 driving 74L
or 1 driving 74LS
• AND-OR select gating
• Shift-right/shift-left registers
• True/complement selection
• AND/OR/EXCLUSIVE-OR selection
Ordering Code:

Order Number Package Number

Package Description

CD4019BCM

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow

CD4019BCN

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Top View
2002 Fairchild Semiconductor Corporation DS005952

CD4019BC

Schematic Diagram

Schematic diagram for 1 of 4 identical stages

CD4019BC

Absolute Maximum Ratings Note 1

Note 2

Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD

Dual-In-Line

Small Outline

Lead Temperature TL Soldering, 10 seconds
−0.5V to +18V −0.5V to VDD +0.5V
−65°C to +150°C
700 mW 500 mW
260°C

Recommended Operation Conditions Note 2

DC Supply Voltage VDD
+3V to +15V

Input Voltage VIN
0V to VDDV

Operating Temperature Range TA
−55°C to +125°C

Note 1 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation.

Note 2 VSS = 0V unless otherwise specified.

DC Electrical Characteristics Note 3

Parameter

Conditions

Quiescent Device

VDD = 5V

Current

VDD = 10V

VDD = 15V

LOW Level
|IO| < 1 µA

Output Voltage

VDD = 5V

VDD = 10V

VDD = 15V

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CD4019BCN Datasheet file may be downloaded here without warranties.

Datasheet ID: CD4019BCN 513557