CD40174BCN
CD40174BCN Datasheet
CD40174BC<br>• CD40175BC Hex D-Type Flip-Flop<br>• Quad D-Type Flip-Flop
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CD40174BCN |
CD40174BCN (pdf) |
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CD40175BCN |
CD40175BCN |
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| CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop CD40174BC • CD40175BC Hex D-Type Flip-Flop • Quad D-Type Flip-Flop The CD40174BC consists of six positive-edge triggered Dtype flip-flops the true outputs from each flip-flop are externally available. The CD40175BC consists of four positiveedge triggered D-type flip-flops both the true and complement outputs from each flip-flop are externally available. All flip-flops are controlled by a common clock and a common clear. Information at the D inputs meeting the set-up time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. The clearing operation, enabled by a negative pulse at Clear input, clears all Q outputs to logical “0” and Q s CD40175BC only to logical All inputs are protected from static discharge by diode clamps to VDD and VSS. s Wide supply voltage range 3V to 15V s High noise immunity VDD typ. s Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74 LS s Equivalent to MC14174B, MC14175B s Equivalent to MM74C174, MM74C175 Ordering Code: Order Number Package Number Package Description CD40174BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD40174BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide CD40175BCM M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow CD40175BCN N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams CD40174B CD40175B Top View Top View 2002 Fairchild Semiconductor Corporation DS005987 CD40174BC • CD40175BC Truth Table Inputs Clear Clock H = HIGH Level L = LOW Level X = Irrelevant = Transition from LOW-to-HIGH level NC = No change Note 1 Q for CD40175B only Outputs Note 1 CD40174BC • CD40175BC Absolute Maximum Ratings Note 2 Note 3 DC Supply Voltage VDD Input Voltage VIN Storage Temperature Range TS Power Dissipation PD Dual-In-Line Small Outline Lead Temperature TL Soldering, 10 seconds −0.5V to +18V −0.5V to VDD VDC −65°C to +150°C 700 mW 500 mW 260°C Recommended Operating Conditions Note 3 DC Supply Voltage VDD 3V to 15 VDC Input Voltage VIN 0V to VDD VDC Operating Temperature Range TA −55°C to +125°C Note 2 “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recommended Operating Conditions” and “Electrical Characteristics” provide conditions for actual device operation. Note 3 VSS = 0V unless otherwise specified. DC Electrical Characteristics Note 3 CD40174BC/CD40175BC Parameter Conditions Quiescent Device |
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