74VHC163MTCX

74VHC163MTCX Datasheet

74VHC163 4-Bit Binary Counter with Synchronous Clear

Part	Datasheet
74VHC163MTCX	74VHC163MTCX (pdf)

Related Parts	Information
74VHC163MX	74VHC163MX
74VHC163MTC	74VHC163MTC
74VHC163SJX	74VHC163SJX
74VHC163M	74VHC163M
74VHC163SJ	74VHC163SJ
74VHC163N	74VHC163N

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74VHC163 4-Bit Binary Counter with Synchronous Clear 74VHC163 4-Bit Binary Counter with Synchronous Clear The VHC163 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The VHC163 is a high-speed synchronous modulo-16 binary counter. This device is synchronously presettable for application in programmable dividers and has two types of Count Enable inputs plus a Terminal Count output for versatility in forming multistage counters. The CLK input is active on the rising edge. Both PE and MR inputs are active on low logic level. Presetting is synchronous to rising edge of CLK and the Clear function of the VHC163 is synchronous to CLK. Two enable inputs ENP and ENT and Carry Output are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. s High speed fMAX = 185 MHz typ at VCC = 5V s Low power dissipation ICC = 4 µA max at TA = 25°C s Synchronous counting and loading s High-speed synchronous expansion s High noise immunity VNIH = VNIL = 28% VCC min s Power down protection is provided on all inputs. s Low noise VOLP = 0.8V max s Pin and function compatible with 74HC163 Ordering Code: Order Number Package Number Package Description 74VHC163M M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74VHC163SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74VHC163MTC MTC16 16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74VHC163N N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC 2002 Fairchild Semiconductor Corporation DS012122 74VHC163 Connection Diagram Pin Descriptions Pin Names CEP CET CP MR PE TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Synchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output Functional Description The VHC163 counts in modulo-16 binary sequence. From state 15 HHHH it increments to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence synchronous reset, parallel load, count-up and hold. Four control Reset MR , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The VHC163 uses D-type edge-triggered flip-flops and changing the MR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count TC output is HIGH when CET is HIGH and counter is in state To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q 2 • Q3 • CET FIGURE 74VHC163 Mode Select Table MR PE CET H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Action on the Rising CEP Clock Edge X Reset Clear X Load Pn Qn H Count Increment X No Change Hold L No Change Hold State Diagram Block Diagram 74VHC163 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Input Diode Current IIK Output Diode Current IOK DC Output Current IOUT DC VCC/GND Current ICC Storage Temperature TSTG Lead Temperature TL Soldering, 10 seconds −0.5V to +7.0V −0.5V to +7.0V −0.5V to VCC + 0.5V −20 mA ±20 mA ±25 mA ±50 mA −65°C to +150°C 260°C Recommended Operating Conditions Note 2 Supply Voltage VCC 2.0V to +5.5V Input Voltage VIN 0V to +5.5V Output Voltage VOUT

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74VHC163 4-Bit Binary Counter with Synchronous Clear
74VHC163 4-Bit Binary Counter with Synchronous Clear

The VHC163 is an advanced high-speed CMOS device fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.

The VHC163 is a high-speed synchronous modulo-16 binary counter. This device is synchronously presettable for application in programmable dividers and has two types of Count Enable inputs plus a Terminal Count output for versatility in forming multistage counters. The CLK input is active on the rising edge. Both PE and MR inputs are active on low logic level. Presetting is synchronous to rising edge of CLK and the Clear function of the VHC163 is synchronous to CLK. Two enable inputs ENP and ENT and Carry Output are provided to enable easy cascading of counters, which facilitates easy implementation of n-bit counters without using external gates.

An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
s High speed fMAX = 185 MHz typ at VCC = 5V s Low power dissipation ICC = 4 µA max at TA = 25°C s Synchronous counting and loading s High-speed synchronous expansion s High noise immunity VNIH = VNIL = 28% VCC min s Power down protection is provided on all inputs. s Low noise VOLP = 0.8V max s Pin and function compatible with 74HC163
Ordering Code:

Order Number Package Number

Package Description
74VHC163M

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74VHC163SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74VHC163MTC

MTC16
16-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74VHC163N

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC
2002 Fairchild Semiconductor Corporation DS012122
74VHC163

Connection Diagram

Pin Descriptions

Pin Names CEP CET CP MR PE TC

Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Synchronous Master Reset Input Parallel Data Inputs Parallel Enable Inputs Flip-Flop Outputs Terminal Count Output

Functional Description

The VHC163 counts in modulo-16 binary sequence. From state 15 HHHH it increments to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence synchronous reset, parallel load, count-up and hold. Four control Reset MR , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.

The VHC163 uses D-type edge-triggered flip-flops and changing the MR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.

The Terminal Count TC output is HIGH when CET is HIGH and counter is in state To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways.

Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min to start its final cycle. Since this final cycle takes 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters.

Logic Equations Count Enable = CEP
• CET
• PE

TC = Q0
• Q1
• Q 2
• Q3
• CET

FIGURE
74VHC163

Mode Select Table

MR PE CET

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Action on the Rising

CEP Clock Edge

X Reset Clear X Load Pn Qn H Count Increment

X No Change Hold

L No Change Hold

State Diagram

Block Diagram
74VHC163

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Input Diode Current IIK Output Diode Current IOK DC Output Current IOUT DC VCC/GND Current ICC Storage Temperature TSTG Lead Temperature TL

Soldering, 10 seconds
−0.5V to +7.0V −0.5V to +7.0V −0.5V to VCC + 0.5V
−20 mA ±20 mA ±25 mA ±50 mA −65°C to +150°C
260°C

Recommended Operating Conditions Note 2

Supply Voltage VCC
2.0V to +5.5V

Input Voltage VIN
0V to +5.5V

Output Voltage VOUT

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Datasheet ID: 74VHC163MTCX 513488