74VCXH16244MTDX
74VCXH16244MTDX Datasheet
74VCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold
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74VCXH16244MTDX |
74VCXH16244MTDX (pdf) |
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74VCXH16244MTD |
74VCXH16244MTD |
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| 74VCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold 74VCXH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold The VCXH16244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble 4-bit controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The VCXH16244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74VCXH16244 is designed for low voltage 1.2V to 3.6V VCC applications with output capability up to 3.6V. The 74VCXH16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.2V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminating the need for external pull-up/pull-down resistors s tPD ns max for 3.0V to 3.6V VCC s Static Drive IOH/IOL r24 mA 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance: Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary Ordering Code: Order Number Package Number Package Description 74VCXH16244G Note 1 Note 2 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide 74VCXH16244MTD Note 2 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 1 Ordering Code “G” indicates Tray. Note 2 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol 2005 Fairchild Semiconductor Corporation DS500230 74VCXH16244 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Names OEn NC Description Output Enable Input Active LOW Bushold Inputs Outputs No Connect FBGA Pin Assignments NC OE1 OE2 NC O5 GND I5 O7 GND I7 O9 GND O14 O13 O15 NC OE4 OE3 NC Truth Tables Inputs OE1 L H Outputs Inputs I4-I7 Outputs O4-O7 L H Z Inputs OE3 L H I8-I11 L H X Outputs Inputs Outputs I12-I15 O12-O15 H HIGH Voltage Level L LOW Voltage Level X Immaterial HIGH or LOW, inputs may not float Z High Impedance 74VCXH16244 Functional Description The 74VCXH16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE out- Logic Diagram puts are controlled by an Output Enable OEn input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. 74VCXH16244 Absolute Maximum Ratings Note 3 |
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