74VCX16722MTD

74VCX16722MTD Datasheet

74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs

Part	Datasheet
74VCX16722MTD	74VCX16722MTD (pdf)

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74VCX16722MTDX	74VCX16722MTDX

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74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs 74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs The VCX16722 low voltage 22-bit register contains twentytwo non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The design has been optimized for use with JEDEC compliant 200 pin DIMM modules. The 74VCX16722 is designed for low voltage 1.65V to 3.6V VCC applications with I/O capability up to 3.6V. The 74VCX16722 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s VCC supply operation s 3.6V tolerant inputs and outputs s tPD CLK to On 3.6ns max for 3.0V to 3.6V VCC 4.6ns max for 2.3V to 2.7V VCC 9.2ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s Meets JEDEC registered module specifications s Static Drive IOH/IOL ±24mA 3.0V ±18mA 2.3V ±6mA 1.65V s Latchup performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model >200V Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74VCX16722MTD MTD64 64-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2005 Fairchild Semiconductor Corporation DS500192 74VCX16722 Connection Diagram Pin Descriptions Pin Names OE CE CLK D0- D21 O0 - O21 Output Enable Input Active LOW Clock Enable Input Active Low Clock Input Data Inputs 3-STATE Outputs Truth Table L or H H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance On = Previous On before LOW-to-HIGH Clock Transition = LOW-to-HIGH Clock Transition Functional Description The VCX16722 contains twenty-two D-type flip-flops with 3-STATE standard outputs. The twenty-two flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-HIGH Clock CLK transition, when the Clock-Enable CE is LOW. The 3-STATE standard outputs are controlled by the Output-Enable OE . When OE is HIGH, the standard outputs are in high impedance mode but this does not interfere with entering new data into the flip-flops. Logic Diagram 74VCX16722 Absolute Maximum Ratings Note 2 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Outputs 3-STATE Outputs Active Note 3 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V VO > VCC DC Output Source/Sink Current IOH/IOL DC VCC or Ground Current per Supply Pin ICC or Ground Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to +4.6V −0.5V to +4.6V −0.5V to VCC + 0.5V −50 mA −50 mA +50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 4 Power Supply Operating 1.65V to 3.6V Data Retention Only 1.2V to 3.6V Input Voltage −0.3V to 3.6V Output Voltage VO Output in Active States Output in 3-STATE 0V to VCC 0V to 3.6V Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V Free Air Operating Temperature TA Minimum Input Edge Rate ±24 mA ±18 mA ±6 mA −40°C to +85°C VIN = 0.8V to 2.0V, VCC = 3.0V

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74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs
74VCX16722 Low Voltage 22-Bit Register with 3.6V Tolerant Inputs and Outputs

The VCX16722 low voltage 22-bit register contains twentytwo non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The design has been optimized for use with JEDEC compliant 200 pin DIMM modules.

The 74VCX16722 is designed for low voltage 1.65V to 3.6V VCC applications with I/O capability up to 3.6V.

The 74VCX16722 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s VCC supply operation s 3.6V tolerant inputs and outputs s tPD CLK to On
3.6ns max for 3.0V to 3.6V VCC 4.6ns max for 2.3V to 2.7V VCC 9.2ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs
s Supports live insertion/withdrawal Note 1 s Meets JEDEC registered module specifications
s Static Drive IOH/IOL ±24mA 3.0V ±18mA 2.3V ±6mA 1.65V
s Latchup performance exceeds 300 mA
s ESD performance:

Human body model > 2000V Machine model >200V

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74VCX16722MTD

MTD64
64-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2005 Fairchild Semiconductor Corporation DS500192
74VCX16722

Connection Diagram

Pin Descriptions

Pin Names

OE CE CLK D0- D21 O0 - O21

Output Enable Input Active LOW Clock Enable Input Active Low Clock Input Data Inputs 3-STATE Outputs

Truth Table

L or H

H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance On = Previous On before LOW-to-HIGH Clock Transition = LOW-to-HIGH Clock Transition

Functional Description

The VCX16722 contains twenty-two D-type flip-flops with 3-STATE standard outputs. The twenty-two flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-HIGH Clock CLK transition, when the Clock-Enable CE is LOW. The 3-STATE standard outputs are controlled by the Output-Enable OE . When OE is HIGH, the standard outputs are in high impedance mode but this does not interfere with entering new data into the flip-flops.

Logic Diagram
74VCX16722

Absolute Maximum Ratings Note 2

Supply Voltage VCC DC Input Voltage VI Output Voltage VO

Outputs 3-STATE Outputs Active Note 3

DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK

VO < 0V VO > VCC DC Output Source/Sink Current IOH/IOL DC VCC or Ground Current per Supply Pin ICC or Ground Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to +4.6V
−0.5V to +4.6V −0.5V to VCC +
0.5V −50 mA
−50 mA +50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 4

Power Supply

Operating
1.65V to 3.6V

Data Retention Only
1.2V to 3.6V

Input Voltage
−0.3V to 3.6V

Output Voltage VO Output in Active States Output in 3-STATE
0V to VCC 0V to 3.6V

Output Current in IOH/IOL VCC = 3.0V to 3.6V VCC = 2.3V to 2.7V VCC = 1.65V to 2.3V

Free Air Operating Temperature TA Minimum Input Edge Rate
±24 mA ±18 mA
±6 mA −40°C to +85°C

VIN = 0.8V to 2.0V, VCC = 3.0V

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Datasheet ID: 74VCX16722MTD 513465