74VCX16601MTDX

74VCX16601MTDX Datasheet

74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

Part	Datasheet
74VCX16601MTDX	74VCX16601MTDX (pdf)

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74VCX16601MTD	74VCX16601MTD

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74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs 74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs The VCX16601 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. The clock can be controlled by the clock-enable CLKENAB and CLKENBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-toLOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The VCX16601 is designed for low voltage 1.4V to 3.6V VCC applications with I/O capability up to 3.6V. The VCX16601 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.4V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD A to B, B to A ns max for 3.0V to 3.6V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s Static Drive IOH/IOL ±24 mA 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latchup performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model >200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74VCX16601GX Note 2 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Preliminary [TAPE and REEL] 74VCX16601MTD Note 3 MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 2 BGA package available in Tape and Reel only. Note 3 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2004 Fairchild Semiconductor Corporation DS500126 74VCX16601 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Names OEAB, OEBA Output Enable Inputs Active LOW LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs CLKENAB, CLKENBA Clock Enable Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs FBGA Pin Assignments A1 OEAB CLKENAB B1 A3 LEAB CLKAB B3 A7 GND A9 GND A12 A11 GND B11 B12 A14 A13 VCC B13 B14 A16 A15 OEBA CLKBA B15 B16 A17 A18 LEBA CLKENBA B18 B17 Truth Table Note 4 Inputs Outputs CLKENAB OEAB LEAB CLKAB An X B0 Note 5 X B0 Note 5 X B0 Note 5 X B0 Note 6 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance Note 4 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Note 5 Output level before the indicated steady-state input conditions were established. Note 6 Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 74VCX16601

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74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74VCX16601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

The VCX16601 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. The clock can be controlled by the clock-enable CLKENAB and CLKENBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-toLOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.

The VCX16601 is designed for low voltage 1.4V to 3.6V VCC applications with I/O capability up to 3.6V.

The VCX16601 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.4V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD A to B, B to A
ns max for 3.0V to 3.6V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s Static Drive IOH/IOL
±24 mA 3.0V VCC s Uses patented noise/EMI reduction circuitry s Latchup performance exceeds 300 mA s ESD performance:

Human body model > 2000V Machine model >200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74VCX16601GX Note 2

BGA54A
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide

Preliminary [TAPE and REEL]
74VCX16601MTD Note 3

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide

Note 2 BGA package available in Tape and Reel only.
Note 3 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2004 Fairchild Semiconductor Corporation DS500126
74VCX16601

Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA Top Thru View

Pin Descriptions

Pin Names

OEAB, OEBA

Output Enable Inputs Active LOW

LEAB, LEBA

Latch Enable Inputs

CLKAB, CLKBA

Clock Inputs

CLKENAB, CLKENBA Clock Enable Inputs

Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs

FBGA Pin Assignments

A1 OEAB CLKENAB B1

A3 LEAB CLKAB B3

A7 GND

A9 GND

A12 A11 GND

B11 B12

A14 A13 VCC

B13 B14

A16 A15 OEBA CLKBA B15 B16

A17 A18 LEBA CLKENBA B18 B17

Truth Table

Note 4

Inputs

Outputs

CLKENAB OEAB LEAB CLKAB An

X B0 Note 5

X B0 Note 5

X B0 Note 5

X B0 Note 6

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance

Note 4 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA.

Note 5 Output level before the indicated steady-state input conditions were established.

Note 6 Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
74VCX16601

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Datasheet ID: 74VCX16601MTDX 513463