74LVX574M

74LVX574M Datasheet

74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74LVX574M	74LVX574M (pdf)

Related Parts	Information
74LVX574SJ	74LVX574SJ
74LVX574SJX	74LVX574SJX
74LVX574MX	74LVX574MX
74LVX574MTCX	74LVX574MTCX
74LVX574MTC	74LVX574MTC

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74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs 74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs The LVX574 is a high-speed octal D-type flip-flop which is controlled by an edge-triggered clock input CP and a buffered common Output Enable OE input. When the OE input is HIGH, the eight outputs are in a high impedance state. The LVX574 is functionally identical to the LVX374 but with inputs and outputs on opposite sides of the package. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems. s Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance Ordering Code: Order Number Package Number Package Description 74LVX574M M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LVX574SJ M20D Pb-Free 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74LVX574MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram Pin Descriptions Pin Names CP OE Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs 2005 Fairchild Semiconductor Corporation DS500050 74LVX574 Functional Description Truth Table The LVX574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The Inputs buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip- H HIGH Voltage Level L LOW Voltage Level flops. X Immaterial High Impedance LOW-to-HIGH Transition Logic Diagram Outputs On H L Z Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVX574 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI DC Input Voltage VI DC Output Diode Current IOK VO VCC 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current ICC or IGND Storage Temperature TSTG Power Dissipation mA to 7V mA to VCC 0.5V r25 mA r75 mA to 180 mW Recommended Operating Conditions Note 2 Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Input Rise and Fall Time 't/'V 2.0V to 3.6V 0V to 5.5V 0V to VCC to 0 ns/V to 100 ns/V Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2 Unused inputs must be held HIGH or LOW. They may not float.

PDF Datasheet Preview

74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
74LVX574 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

The LVX574 is a high-speed octal D-type flip-flop which is controlled by an edge-triggered clock input CP and a buffered common Output Enable OE input. When the OE input is HIGH, the eight outputs are in a high impedance state. The LVX574 is functionally identical to the LVX374 but with inputs and outputs on opposite sides of the package. The inputs tolerate up to 7V allowing interface of 5V systems to 3V systems.
s Input voltage translation from 5V to 3V s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:

Order Number Package Number

Package Description
74LVX574M

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74LVX574SJ

M20D

Pb-Free 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74LVX574MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B.

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names CP OE

Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs
2005 Fairchild Semiconductor Corporation DS500050
74LVX574

Functional Description

Truth Table

The LVX574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The

Inputs
buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is

HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-

H HIGH Voltage Level L LOW Voltage Level
flops.

X Immaterial

High Impedance LOW-to-HIGH Transition

Logic Diagram

Outputs On H L Z

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVX574

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI DC Input Voltage VI DC Output Diode Current IOK

VO VCC 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current

ICC or IGND Storage Temperature TSTG Power Dissipation
mA to 7V
mA to VCC 0.5V
r25 mA
r75 mA to
180 mW

Recommended Operating Conditions Note 2

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Input Rise and Fall Time 't/'V
2.0V to 3.6V 0V to 5.5V 0V to VCC
to 0 ns/V to 100 ns/V

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2 Unused inputs must be held HIGH or LOW. They may not float.

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Datasheet ID: 74LVX574M 513449