AT17LV020A-10JI

AT17LV020A-10JI Datasheet


The AT17C020A and AT17LV020A high-density AT17A Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for programming Altera devices. The AT17A Series is packaged in the popular 20-lead PLCC. The AT17A Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17A Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a feature of the AT17A Series, the user can select the polarity of the reset function by programming internal EEPROM bytes. The AT17A parts generate their own internal clock and can be used as a system “master” for loading the FPGA devices.

Part Datasheet
AT17LV020A-10JI AT17LV020A-10JI AT17LV020A-10JI (pdf)
Related Parts Information
AT17C020A-10JI AT17C020A-10JI AT17C020A-10JI
AT17C020A-10JC AT17C020A-10JC AT17C020A-10JC
AT17LV020A-10JC AT17LV020A-10JC AT17LV020A-10JC
PDF Datasheet Preview
• Serial EEPROM Family for Configuring Altera Devices
• Simple Interface to SRAM FPGAs
• EE Programmable 2M-bit Serial Memories Designed to Store Configuration Programs
for Field Programmable Gate Arrays FPGAs
• Cascadable Read Back to Support Additional Configurations or Future

Higher-density Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in the Space-efficient Surface-mount PLCC Package
• In-System Programmable Via 2-wire Bus
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V ± 5% LV and 5V ± 5% C Versions
• System-friendly READY Pin

The AT17C020A and AT17LV020A high-density AT17A Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for programming Altera devices. The AT17A Series is packaged in the popular 20-lead PLCC. The AT17A Series family uses a simple serial-access procedure to configure one or more FPGA devices. The AT17A Series organization supplies enough memory to configure one or multiple smaller FPGAs. Using a feature of the AT17A Series, the user can select the polarity of the reset function by programming internal EEPROM bytes. The AT17A parts generate their own internal clock and can be used as a system “master” for loading the FPGA devices.

The Atmel devices also support a system-friendly READY pin. The READY pin is used to simplify system power-up considerations.

The AT17A Series Configurators can be programmed with industry-standard programmers, or Atmel’s ATDH2200E Programming Kit.

FPGA Configuration EEPROM Memory
2-Mbit Altera Pinout

AT17C020A AT17LV020A

Pin Configurations

PLCC
3 NC 2 DATA 1 NC 20 VCC 19 NC

DCLK 4 NC 5 NC 6 NC 7 OE 8
18 SER_EN 17 NC 16 NC 15 READY 14 NC
nCS 9 GND 10

NC 11 A2 nCASC 12

NC 13

Block Diagram

SER_EN

OSC CONTROL

POWER ON RESET

PROGRAMMING MODE LOGIC

ROW ADDRESS COUNTER

BIT COUNTER

PROGRAMMING DATA SHIFT REGISTER

ROW DECODER

EEPROM CELL

MATRIX

COLUMN DECODER

DCLK READY
nCS nCASC A2

DATA

Device Configuration

The control signals for the configuration EEPROM-nCS, OE, and DCLK-interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration EEPROM without requiring an external intelligent controller.

The configuration EEPROM’s OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address counter and the oscillator. When OE is driven Low, the configuration EEPROM resets its address counter and tri-states its DATA pin. The nCS pin also controls the output of the AT17A Series Configurator. If nCS is held High after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven Low, the counter and the DATA output pin are enabled. When OE is
driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS.

When the Configurator has driven out all of its data and nCASC is driven Low, the device tri-states the DATA pin to avoid contention with other Configurators. Upon power-up, the address counter is automatically reset.

The READY pin is available as an open-collector indicator of the device’s reset status it is driven Low while the device is in its power-on reset cycle and released tri-stated when the cycle is complete.

This document discusses the EPF10K device interface. For more details or information on other Altera applications, please reference the “AT17A Series Conversions from Altera FPGA Serial Configuration Memories” application note.

AT17C/LV020A

AT17C/LV020A
Ordering Information - 5V Devices

Memory Size
Ordering Code AT17C020A-10JC

AT17C020A-10JI
Ordering Information - 3.3V Devices

Memory Size
Ordering Code AT17LV020A-10JC

AT17LV020A-10JI

Note Use 2M density parts to replace Altera EPC2.

AT17C/LV020A

Package 20J

Package 20J

Operation Range Commercial 0°C to 70°C Industrial
-40°C to 85°C

Operation Range Commercial 0°C to 70°C Industrial
-40°C to 85°C

Package Type
20-lead, Plastic J-leaded Chip Carrier PLCC

Packaging Information
20J, 20-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

JEDEC STANDARD MS-018 AA

AT17C/LV020A

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Datasheet ID: AT17LV020A-10JI 518855