74LVX161284AMTX

74LVX161284AMTX Datasheet

74LVX161284A Low Voltage IEEE 161284 Translating Transceiver

Part	Datasheet
74LVX161284AMTX	74LVX161284AMTX (pdf)

Related Parts	Information
74LVX161284AMTD	74LVX161284AMTD

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74LVX161284A Low Voltage IEEE 161284 Translating Transceiver 74LVX161284A Low Voltage IEEE 161284 Translating Transceiver The LVX161284A contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard, with the exception of output slew rate, and is intended to be used in an Extended Capabilities Port mode ECP . The pinout allows for easy connection from the Peripheral A-side to the Host cable side . Outputs on the cable side can be configured to be either open drain or high drive ± 14 mA and are connected to a separate power supply pin to allow these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs except HLH and outputs on the cable side contain internal pull-up resistors connected to the supply to provide proper termination and pull-ups for open drain mode. Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the transceiver pins. s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals with the exception of output slew rate s Translation capability allows outputs on the cable side to interface with 5V signals s All inputs have hysteresis to provide noise margin s B and Y output resistance optimized to drive external cable s B and Y outputs in high impedance mode during power down s Inputs and outputs on cable side have internal pull-up resistors s Flow-through pin configuration allows easy interface between the “Peripheral and Host” s Replaces the function of two 2 74ACT1284 devices Ordering Code Order Number Package Number Package Description 74LVX161284AMTD MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names High Drive Enable Input Active HIGH Direction Control Input PLHIN PLH Inputs or Outputs Inputs or Outputs Inputs Outputs Inputs Peripheral Logic HIGH Input Peripheral Logic HIGH Output HLHIN HLH Host Logic HIGH Input Host Logic HIGH Output 2000 Fairchild Semiconductor Corporation DS500204 74LVX161284A Logic Symbol Truth Table Note 1 Open Drain Outputs Note 2 Open Drain Outputs Logic Diagram Inputs DIR HD Outputs Data to and Data to Note 1 Data to PLH Open Drain Mode Data to and Data to Data to Data to Note 2 Data to Note 1 Data to PLH Open Drain Mode Data to Data to Data to 74LVX161284A Absolute Maximum Ratings Note 3 Supply Voltage Recommended Operating Conditions VCC Must Be VCC Input Voltage 4 PLHIN, DIR, HD HLHIN −0.5V to +4.6V −0.5V to +7.0V −0.5V to VCC + 0.5V −0.5V to +5.5V DC −2.0V to +7.0V* 40 ns Transient Supply Voltage VCC DC Input Voltage VI Open Drain Voltage VO Operating Temperature TA 3.0V to 3.6V 3.0V to 5.5V 0V to VCC 0V to 5.5V −40°C to +85°C Output Voltage VO HLH PLH −0.5V to VCC +0.5V −0.5V to +5.5V DC −2.0V to +7.0V *40 ns Transient DC Output Current IO HLH PLH Output LOW ±25 mA ±50 mA 84 mA PLH Output HIGH −50 mA Input Diode Current 4 DIR, HD, PLH, HLH,

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74LVX161284A Low Voltage IEEE 161284 Translating Transceiver
74LVX161284A Low Voltage IEEE 161284 Translating Transceiver

The LVX161284A contains eight bidirectional data buffers and eleven control/status buffers to implement a full IEEE 1284 compliant interface. The device supports the IEEE 1284 standard, with the exception of output slew rate, and is intended to be used in an Extended Capabilities Port mode ECP . The pinout allows for easy connection from the Peripheral A-side to the Host cable side .

Outputs on the cable side can be configured to be either open drain or high drive ± 14 mA and are connected to a separate power supply pin to allow these outputs to be driven by a higher supply voltage than the A-side. The pull-up and pull-down series termination resistance of these outputs on the cable side is optimized to drive an external cable. In addition, all inputs except HLH and outputs on the cable side contain internal pull-up resistors connected to the supply to provide proper termination and pull-ups for open drain mode.

Outputs on the Peripheral side are standard low-drive CMOS outputs designed to interface with 3V logic. The DIR input controls data flow on the transceiver pins.
s Supports IEEE 1284 Level 1 and Level 2 signaling standards for bidirectional parallel communications between personal computers and printing peripherals with the exception of output slew rate
s Translation capability allows outputs on the cable side to interface with 5V signals
s All inputs have hysteresis to provide noise margin s B and Y output resistance optimized to drive external
cable s B and Y outputs in high impedance mode during power
down s Inputs and outputs on cable side have internal pull-up
resistors s Flow-through pin configuration allows easy interface
between the “Peripheral and Host” s Replaces the function of two 2 74ACT1284 devices
Ordering Code

Order Number

Package Number

Package Description
74LVX161284AMTD

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

High Drive Enable Input Active HIGH

Direction Control Input

PLHIN PLH

Inputs or Outputs Inputs or Outputs Inputs Outputs Inputs Peripheral Logic HIGH Input Peripheral Logic HIGH Output

HLHIN HLH

Host Logic HIGH Input Host Logic HIGH Output
2000 Fairchild Semiconductor Corporation DS500204
74LVX161284A

Logic Symbol

Truth Table

Note 1 Open Drain Outputs Note 2 Open Drain Outputs

Logic Diagram

Inputs

DIR HD

Outputs

Data to and Data to Note 1 Data to PLH Open Drain Mode Data to and Data to Data to Data to Note 2 Data to Note 1 Data to PLH Open Drain Mode Data to Data to Data to
74LVX161284A

Absolute Maximum Ratings Note 3

Supply Voltage

Recommended Operating Conditions

VCC Must Be VCC Input Voltage 4 PLHIN, DIR, HD HLHIN
−0.5V to +4.6V −0.5V to +7.0V
−0.5V to VCC + 0.5V −0.5V to +5.5V DC
−2.0V to +7.0V* *40 ns Transient

Supply Voltage

VCC DC Input Voltage VI Open Drain Voltage VO Operating Temperature TA
3.0V to 3.6V 3.0V to 5.5V
0V to VCC 0V to 5.5V −40°C to +85°C

Output Voltage VO HLH PLH
−0.5V to VCC +0.5V −0.5V to +5.5V DC
−2.0V to +7.0V* *40 ns Transient

DC Output Current IO HLH PLH Output LOW
±25 mA ±50 mA
84 mA

PLH Output HIGH
−50 mA

Input Diode Current 4 DIR, HD, PLH, HLH,

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Datasheet ID: 74LVX161284AMTX 513445