74LVTH646MTC

74LVTH646MTC Datasheet

74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs

Part	Datasheet
74LVTH646MTC	74LVTH646MTC (pdf)

Related Parts	Information
74LVTH646WMX	74LVTH646WMX
74LVTH646WM	74LVTH646WM
74LVTH646MTCX	74LVTH646MTCX

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74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs 74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs The LVTH646 consists of registered bus transceiver circuits, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-toHIGH transition of the appropriate clock pin CPAB or CPBA . See Functional Description The LVTH646 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The bus transceivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH646 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 646 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVTH646WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LVTH646MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code. Logic Symbols IEEE/IEC 2000 Fairchild Semiconductor Corporation DS012017 74LVTH646 Connection Diagram Pin Descriptions Pin Names CPAB, CPBA SAB, SBA OE DIR Description Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input Truth Table Note 1 Inputs Data I/O OE DIR CPAB CPBA SAB SBA Function H or L H = HIGH Voltage Level L = LOW Voltage Level Isolation Input Input Clock An Data into A Register Clock Bn Data into B Register An to Time Transparent Mode Input Output Clock An Data into A Register A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn Bn to Time Transparent Mode Output Input Clock Bn Data into B Register B Register to An Stored Mode X = Immaterial Clock Bn Data into B Register and Output to An = LOW-to-HIGH Transition Note 1 The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVTH646 Functional Description In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select SAB, SBA controls can multiplex stored and real-time. The examples below demonstrate the four fundamental busmanagement functions that can be performed. The direction control DIR determines which bus will receive data when OE is LOW. In the isolation mode OE HIGH , A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two busses, A or B, may be driven at a time. Real-Time Transfer Bus B to Bus A Real-Time Transfer Bus B to Bus A

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74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs
74LVTH646 Low Voltage Octal Transceiver/Register with 3-STATE Outputs

The LVTH646 consists of registered bus transceiver circuits, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-toHIGH transition of the appropriate clock pin CPAB or CPBA . See Functional Description

The LVTH646 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

The bus transceivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH646 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs
s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 646 s Latch-up performance exceeds 500 mA s ESD performance:

Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
Ordering Code:

Order Number Package Number

Package Description
74LVTH646WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74LVTH646MTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.

Logic Symbols

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS012017
74LVTH646

Connection Diagram

Pin Descriptions

Pin Names

CPAB, CPBA SAB, SBA OE DIR

Description Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input

Truth Table

Note 1

Inputs

Data I/O

OE DIR CPAB CPBA SAB SBA

Function

H or L

H = HIGH Voltage Level L = LOW Voltage Level

Isolation

Input

Input Clock An Data into A Register

Clock Bn Data into B Register

An to Time Transparent Mode

Input Output Clock An Data into A Register

A Register to Bn Stored Mode

Clock An Data into A Register and Output to Bn

Bn to Time Transparent Mode

Output

Input Clock Bn Data into B Register

B Register to An Stored Mode

X = Immaterial

Clock Bn Data into B Register and Output to An = LOW-to-HIGH Transition

Note 1 The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVTH646

Functional Description

In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select SAB, SBA controls can multiplex stored and real-time. The examples below demonstrate the four fundamental busmanagement functions that can be performed.

The direction control DIR determines which bus will receive data when OE is LOW. In the isolation mode OE HIGH , A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two busses, A or B, may be driven at a time.

Real-Time Transfer Bus B to Bus A

Real-Time Transfer Bus B to Bus A

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Datasheet ID: 74LVTH646MTC 513442