74LVTH543WMX

74LVTH543WMX Datasheet

74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs

Part	Datasheet
74LVTH543WMX	74LVTH543WMX (pdf)

Related Parts	Information
74LVTH543MTC	74LVTH543MTC
74LVTH543MTCX	74LVTH543MTCX
74LVTH543WM	74LVTH543WM

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74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs 74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs The LVTH543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The LVTH543 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. This octal registered transceiver is designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH543 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 543 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVTH543WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LVTH543MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names OEAB, OEBA LEAB, LEBA CEAB, CEBA Output Enable Inputs Latch Enable Inputs Chip Enable Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs 2000 Fairchild Semiconductor Corporation DS012448 74LVTH543 Logic Symbols IEEE/IEC Logic Diagram Functional Description The LVTH543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable CEAB input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB LOW, a low signal on LEAB input makes the A to B latches transparent a subsequent LOW-to-HIGH transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA. Data I/O Control Table Inputs CEAB LEAB OEAB Latch Status Output Buffers Latched High Z Latched Transparent High Z Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note A-to-B data flow shown B-to-A flow control is the same, except using CEBA, LEBA, and OEBA. Please not that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVTH543 Absolute Maximum Ratings Note 1 VCC VI VO Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value to −50 −50 64 128 ±64 ±128 −65 to +150 Conditions Output in 3-STATE Output in HIGH or LOW State Note 2 VI < GND VO < GND VO > VCC Output at HIGH State VO > VCC Output at LOW State Units V mA mA °C

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74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs
74LVTH543 Low Voltage Octal Registered Transceiver with 3-STATE Outputs

The LVTH543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow.

The LVTH543 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

This octal registered transceiver is designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH543 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs
s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 543 s Latch-up performance exceeds 500 mA s ESD performance:

Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
Ordering Code:

Order Number Package Number

Package Description
74LVTH543WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74LVTH543MTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names OEAB, OEBA LEAB, LEBA CEAB, CEBA

Output Enable Inputs Latch Enable Inputs Chip Enable Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
2000 Fairchild Semiconductor Corporation DS012448
74LVTH543

Logic Symbols

IEEE/IEC

Logic Diagram

Functional Description

The LVTH543 contains two sets of D-type latches, with separate input and output controls for each. For data flow from A to B, for example, the A to B Enable CEAB input must be LOW in order to enter data from the A Port or take data from the B Port as indicated in the Data I/O Control Table. With CEAB LOW, a low signal on LEAB input makes the A to B latches transparent a subsequent LOW-to-HIGH transition of the LEAB line puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the B output buffers are active and reflect the data present on the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA.

Data I/O Control Table

Inputs CEAB LEAB

OEAB

Latch Status

Output Buffers

Latched

High Z

Latched

Transparent

High Z

Driving

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Note A-to-B data flow shown B-to-A flow control is the same, except using CEBA, LEBA, and OEBA.

Please not that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVTH543

Absolute Maximum Ratings Note 1

VCC VI VO

Parameter Supply Voltage DC Input Voltage DC Output Voltage

DC Input Diode Current

DC Output Diode Current

DC Output Current

ICC IGND TSTG

DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Value to
−50 −50 64 128 ±64 ±128 −65 to +150

Conditions

Output in 3-STATE Output in HIGH or LOW State Note 2 VI < GND VO < GND VO > VCC Output at HIGH State VO > VCC Output at LOW State

Units V mA
mA °C

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Datasheet ID: 74LVTH543WMX 513441