74LVTH273SJ

74LVTH273SJ Datasheet

74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear

Part	Datasheet
74LVTH273SJ	74LVTH273SJ (pdf)

Related Parts	Information
74LVTH273SJX	74LVTH273SJX
74LVTH273MTCX	74LVTH273MTCX
74LVTH273WMX	74LVTH273WMX
74LVTH273WM	74LVTH273WM
74LVTH273MTC	74LVTH273MTC

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74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear January 2008 • Input and output interface capability to systems at 5V VCC • Bushold on the data inputs eliminate the need for external pull-up resistors to hold unused inputs • Outputs source/sink • Functionally compatible with the 74 series 273 • Latch-up performance exceeds 500mA • ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock CP and Clear CLR are common to all flip-flops. The state of each D-type input, one setup time before the positive clock transition, is transferred to the corresponding flip-flop's output. The LVTH273 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal flip-flops are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH273 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. Ordering Information Order Number 74LVTH273WM 74LVTH273SJ 74LVTH273MTC Package Number M20B M20D MTC20 Package Description 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names CP CLR Description Data Inputs Clock Pulse Input Clear Outputs Functional Description The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. When the Clock is either HIGH or LOW, the D-input signal has no effect at the output. When the Clear CLR is LOW, all Outputs will be forced LOW. Logic Diagram Truth Table Inputs Outputs H or L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Oo = Previous Oo before HIGH-to-LOW of CP Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1999 Fairchild Semiconductor Corporation 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter Supply Voltage DC Input Voltage DC Output Voltage, Output in HIGH or LOW State 1 DC Input Diode Current, VI < GND DC Output Diode Current, VO < GND DC Output Current, VO > VCC Output at HIGH State Output at LOW State ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Note IO Absolute Maximum Rating must be observed. Rating to +4.6V to +7.0V to +7.0V 64mA 128mA ±64mA ±128mA to +150°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. VCC VI IOH IOL TA / Parameter Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = VCC = 3.0V

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74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear
74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear

January 2008
• Input and output interface capability to systems at 5V VCC
• Bushold on the data inputs eliminate the need for external pull-up resistors to hold unused inputs
• Outputs source/sink
• Functionally compatible with the 74 series 273
• Latch-up performance exceeds 500mA
• ESD performance:

Human-body model > 2000V Machine model > 200V Charged-device model > 1000V

The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock CP and Clear CLR are common to all flip-flops.

The state of each D-type input, one setup time before the positive clock transition, is transferred to the corresponding flip-flop's output.

The LVTH273 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These octal flip-flops are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH273 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
Ordering Information

Order Number 74LVTH273WM 74LVTH273SJ 74LVTH273MTC

Package Number

M20B M20D MTC20

Package Description 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.
74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Description

Pin Names CP CLR

Description Data Inputs Clock Pulse Input Clear Outputs

Functional Description

The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. When the Clock is either HIGH or LOW, the D-input signal has no effect at the output. When the Clear CLR is LOW, all Outputs will be forced LOW.

Logic Diagram

Truth Table

Inputs

Outputs

H or L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= LOW-to-HIGH Transition Oo = Previous Oo before HIGH-to-LOW of CP

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1999 Fairchild Semiconductor Corporation
74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

Supply Voltage

DC Input Voltage

DC Output Voltage, Output in HIGH or LOW State 1

DC Input Diode Current, VI < GND

DC Output Diode Current, VO < GND

DC Output Current, VO > VCC

Output at HIGH State

Output at LOW State

ICC IGND TSTG

DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Note IO Absolute Maximum Rating must be observed.

Rating to +4.6V to +7.0V to +7.0V
64mA 128mA ±64mA ±128mA to +150°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

VCC VI IOH IOL TA /

Parameter Supply Voltage Input Voltage HIGH-Level Output Current LOW-Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = VCC = 3.0V

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Datasheet ID: 74LVTH273SJ 513437