74LVTH16652MEAX

74LVTH16652MEAX Datasheet

74LVTH16652 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs

Part	Datasheet
74LVTH16652MEAX	74LVTH16652MEAX (pdf)

Related Parts	Information
74LVTH16652MEA	74LVTH16652MEA
74LVTH16652MTDX	74LVTH16652MTDX
74LVTH16652MTD	74LVTH16652MTD

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74LVTH16652 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs 74LVTH16652 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs The LVTH16652 consists of sixteen bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins OEAB, OEBA are provided to control the transceiver function see Functional Description . The LVTH16652 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The transceivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16652 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 16652 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVTH16652MEA MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74LVTH16652MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. 2000 Fairchild Semiconductor Corporation DS012024 74LVTH16652 Connection Diagram Pin Descriptions Pin Names CPABn, CPBAn SABn, SBAn OEABn, OEBAn Description Data Register A Inputs/ 3-STATE Outputs Data Register B Inputs/ 3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Inputs Truth Table Note 1 Inputs Inputs/Outputs Operating Mode OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 A0 thru A7 B0 thru B7 H or L H or L X X Input Input Isolation Store A and B Data H or L X X Input Not Specified Store A, Hold B X Input Output Store A in Both Registers X H or L X Not Specified Input Hold A, Store B X Output Input Store B in Both Registers L Output Input Real-Time B Data to A Bus X H or L X Store B Data to A Bus X Input Output Real-Time A Data to B Bus H or L X Stored A Data to B Bus

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74LVTH16652 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs
74LVTH16652 Low Voltage 16-Bit Transceiver/Register with 3-STATE Outputs

The LVTH16652 consists of sixteen bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to the HIGH logic level. Output Enable pins OEAB, OEBA are provided to control the transceiver function see Functional Description .

The LVTH16652 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

The transceivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16652 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs
s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 16652 s Latch-up performance exceeds 500 mA s ESD performance:

Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
Ordering Code:

Order Number Package Number

Package Description
74LVTH16652MEA

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74LVTH16652MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
2000 Fairchild Semiconductor Corporation DS012024
74LVTH16652

Connection Diagram

Pin Descriptions

Pin Names

CPABn, CPBAn SABn, SBAn OEABn, OEBAn

Description Data Register A Inputs/ 3-STATE Outputs Data Register B Inputs/ 3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Inputs

Truth Table

Note 1

Inputs

Inputs/Outputs

Operating Mode

OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 A0 thru A7 B0 thru B7

H or L H or L X

X Input

Input

Isolation

Store A and B Data

H or L X

X Input

Not Specified Store A, Hold B

X Input

Output

Store A in Both Registers

X H or L

X Not Specified Input

Hold A, Store B

X Output

Input

Store B in Both Registers

L Output

Input

Real-Time B Data to A Bus

X H or L X

Store B Data to A Bus

X Input

Output

Real-Time A Data to B Bus

H or L X

Stored A Data to B Bus

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Datasheet ID: 74LVTH16652MEAX 513435