74LVQ374SCX

74LVQ374SCX Datasheet

74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74LVQ374SCX	74LVQ374SCX (pdf)

Related Parts	Information
74LVQ374SJ	74LVQ374SJ
74LVQ374SJX	74LVQ374SJX
74LVQ374QSCX	74LVQ374QSCX
74LVQ374QSC	74LVQ374QSC
74LVQ374SC	74LVQ374SC

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74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs 74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs The LVQ374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flipflops. s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ and QSOP pack- ages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into s 4 kV minimum ESD immunity s Buffered positive edge-triggered clock s 3-STATE outputs drive bus lines or buffer memory address registers Ordering Code: Order Number Package Number Package Description 74LVQ374SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LVQ374SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74LVQ374QSC MQA20 20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names CP OE Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Truth Table Inputs Dn H L H = HIGH Voltage Level = Immaterial = LOW-to-HIGH Transition Outputs L = LOW Voltage Level Z = High Impedance 2001 Fairchild Semiconductor Corporation DS011360 74LVQ374 Functional Description The LVQ374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. Logic Diagram With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVQ374 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±400 mA −65°C to +150°C ±300 mA Recommended Operating Conditions Note 2 Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 3.0V 2.0V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

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74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

The LVQ374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flipflops.
s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ and QSOP pack-
ages s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into s 4 kV minimum ESD immunity s Buffered positive edge-triggered clock s 3-STATE outputs drive bus lines or buffer memory
address registers
Ordering Code:

Order Number Package Number

Package Description
74LVQ374SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74LVQ374SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74LVQ374QSC

MQA20
20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names CP OE

Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs

Truth Table

Inputs

Dn H L

H = HIGH Voltage Level
= Immaterial = LOW-to-HIGH Transition

Outputs

L = LOW Voltage Level Z = High Impedance
2001 Fairchild Semiconductor Corporation DS011360
74LVQ374

Functional Description

The LVQ374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition.

Logic Diagram

With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVQ374

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current

ICC or IGND Storage Temperature TSTG DC Latch-Up Source or

Sink Current
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±400 mA −65°C to +150°C
±300 mA

Recommended Operating Conditions Note 2

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN from 0.8V to 2.0V VCC 3.0V
2.0V to 3.6V 0V to VCC 0V to VCC
−40°C to +85°C
125 mV/ns

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

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Datasheet ID: 74LVQ374SCX 513416