74LVQ373SCX
74LVQ373SCX Datasheet
74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs
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74LVQ373SCX |
74LVQ373SCX (pdf) |
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74LVQ373QSCX |
74LVQ373QSCX |
74LVQ373SJ |
74LVQ373SJ |
74LVQ373SJX |
74LVQ373SJX |
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74LVQ373SC |
74LVQ373SC |
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74LVQ373QSC |
74LVQ373QSC |
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| 74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs 74LVQ373 Low Voltage Octal Transparent Latch with 3-STATE Outputs The LVQ373 consists of eight latches with 3-STATE outputs for bus organized system applications. The latches appear transparent to the data when Latch Enable LE is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ and QSOP packages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into s 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74LVQ373SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LVQ373SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74LVQ373QSC MQA20 20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs Truth Table Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH to Low transition of Latch Enable 2001 Fairchild Semiconductor Corporation DS011359 74LVQ373 Functional Description The LVQ373 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW, the latches store the information that was present on the D-type inputs a setup time preceding the Logic Diagram HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVQ373 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±400 mA −65°C to +150°C ±300 mA Recommended Operating Conditions Note 2 Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 3.0V 2.0V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C |
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