74LCX841WM

74LCX841WM Datasheet

74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs

Part	Datasheet
74LCX841WM	74LCX841WM (pdf)

Related Parts	Information
74LCX841MSA	74LCX841MSA
74LCX841MSAX	74LCX841MSAX
74LCX841MTC	74LCX841MTC
74LCX841MTCX	74LCX841MTCX
74LCX841WMX	74LCX841WMX

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74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs 74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs The LCX841 consists of ten latches with 3-STATE outputs for bus organized system applications. The device is designed for low voltage 2.5V or 3.3V VCC applications with capability of interfacing to a 5V signal environment. The LCX841 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. s 5V tolerant inputs and outputs s 2.3V − 3.6V VCC specifications provided s ns tPD max VCC = 3.3V , 10 µA ICC max s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s ±24 mA output drive VCC = 3.0V s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human Body Model > 2000V Machine Model > 200V Note 1 To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX841WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LCX841MSA MSA24 24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74LCX841MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2001 Fairchild Semiconductor Corporation DS012575 74LCX841 Pin Descriptions Truth Table Pin Names LE OE Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs Functional Description The LCX841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. Logic Diagram Inputs OE LE D H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impendance NC = No Change Internal Output Function High Z High Z High Z Latched Transparent Latched On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LCX841 Absolute Maximum Ratings Note 2 Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current IO ICC IGND TSTG DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value to VCC + −50 −50 +50 ±50 ±100 ±100 −65 to +150 Conditions Output in 3-STATE Output in HIGH or LOW State Note 3 VI < GND VO < GND VO > VCC Units V mA °C Recommended Operating Conditions Note 4 Parameter Units Supply Voltage

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74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs
74LCX841 Low Voltage 10-Bit Transparent Latch with 5V Tolerant Inputs and Outputs

The LCX841 consists of ten latches with 3-STATE outputs for bus organized system applications. The device is designed for low voltage 2.5V or 3.3V VCC applications with capability of interfacing to a 5V signal environment.

The LCX841 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
s 5V tolerant inputs and outputs s 2.3V − 3.6V VCC specifications provided s ns tPD max VCC = 3.3V , 10 µA ICC max s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s ±24 mA output drive VCC = 3.0V s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:

Human Body Model > 2000V Machine Model > 200V

Note 1 To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74LCX841WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74LCX841MSA

MSA24
24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74LCX841MTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2001 Fairchild Semiconductor Corporation DS012575
74LCX841

Pin Descriptions

Truth Table

Pin Names LE OE

Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs

Functional Description

The LCX841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition.

Logic Diagram

Inputs

OE LE D

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impendance NC = No Change

Internal Output

Function

High Z High Z High Z Latched Transparent Latched

On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LCX841

Absolute Maximum Ratings Note 2

Parameter

Supply Voltage

DC Input Voltage

DC Output Voltage

DC Input Diode Current

DC Output Diode Current

IO ICC IGND TSTG

DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Value to VCC +
−50 −50 +50 ±50 ±100 ±100 −65 to +150

Conditions

Output in 3-STATE Output in HIGH or LOW State Note 3 VI < GND VO < GND VO > VCC

Units V
mA °C

Recommended Operating Conditions Note 4

Parameter

Units

Supply Voltage

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Datasheet ID: 74LCX841WM 513391