74F843SPC

74F843SPC Datasheet

74F843 9-Bit Transparent Latch

Part	Datasheet
74F843SPC	74F843SPC (pdf)

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74F843 9-Bit Transparent Latch 74F843 9-Bit Transparent Latch The 74F843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. s 3-STATE output Ordering Code: Order Number Package Number Package Description 74F843SCX M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Logic Symbols Connection Diagram IEEE 2004 Fairchild Semiconductor Corporation DS009453 74F843 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Data Inputs Output Enable Input 20 µA/−0.6 mA 20 µA/−0.6 mA Latch Enable 20 µA/−0.6 mA Clear 20 µA/−0.6 mA Preset 20 µA/−0.6 mA 3-STATE Data Outputs 150/40 −3 mA/24 mA Functional Description The 74F843 consists of nine D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to the LE and OE pins, the 74F843 has a Clear CLR pin and a Preset PRE . These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the Outputs are HIGH if OE is LOW. Preset overrides CLR. Function Table Inputs CLR PRE OE LE HHX X HHHH HHH L HH L H HH L H HHL L HL L X LHLX LLLX LHHL HLHL H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Internal Output Function High Z High Z High Z Latched L Transparent H Transparent Latched Preset

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74F843 9-Bit Transparent Latch
74F843 9-Bit Transparent Latch

The 74F843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity.
s 3-STATE output
Ordering Code:

Order Number Package Number

Package Description
74F843SCX

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide

Logic Symbols

Connection Diagram

IEEE
2004 Fairchild Semiconductor Corporation DS009453
74F843

Unit Loading/Fan Out

Pin Names

U.L.

Input IIH/IIL

HIGH/LOW Output IOH/IOL

Data Inputs Output Enable Input
20 µA/−0.6 mA 20 µA/−0.6 mA

Latch Enable
20 µA/−0.6 mA

Clear
20 µA/−0.6 mA

Preset
20 µA/−0.6 mA
3-STATE Data Outputs 150/40 −3 mA/24 mA

Functional Description

The 74F843 consists of nine D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to the LE and OE pins, the 74F843 has a Clear CLR pin and a Preset PRE . These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the Outputs are HIGH if OE is LOW. Preset overrides CLR.

Function Table

Inputs

CLR PRE OE LE HHX X HHHH HHH L HH L H HH L H HHL L HL L X LHLX LLLX LHHL HLHL

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change

Internal Output

Function

High Z

High Z

High Z

Latched

L Transparent

H Transparent

Latched

Preset

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Datasheet ID: 74F843SPC 513378