74F821SCX

74F821SCX Datasheet

74F821 10-Bit D-Type Flip-Flop

Part	Datasheet
74F821SCX	74F821SCX (pdf)

Related Parts	Information
74F821SC	74F821SC
74F821SPC	74F821SPC

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74F821 10-Bit D-Type Flip-Flop 74F821 10-Bit D-Type Flip-Flop The 74F821 is a 10-bit D-type flip-flop with 3-STATE true outputs arranged in a broadside pinout. s 3-STATE Outputs Ordering Code: Order Number Package Number Package Description 74F821SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F821SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009595 74F821 Unit Loading/Fan Out Pin Names Data Inputs Output Enable 3-STATE Input Clock Input 3-STATE Outputs Functional Description The 74F821 consists of ten D-type edge-triggered flipflops. This device has 3-STATE true outputs for bus systems organized in a broadside pinning. The buffered Clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the content of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Logic Diagram U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 150/40 mA/24 mA 20 mA Function Table Inputs Internal Output OE CP D Function H X NC Z Hold X L H L H NC H L H L Z Hold Z Load Z Load L Data Available H Data Available L H X NC NC No Change in Data L X NC NC No Change in Data L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Transition NC = No Change Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F821 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C

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74F821 10-Bit D-Type Flip-Flop
74F821 10-Bit D-Type Flip-Flop

The 74F821 is a 10-bit D-type flip-flop with 3-STATE true outputs arranged in a broadside pinout.
s 3-STATE Outputs
Ordering Code:

Order Number Package Number

Package Description
74F821SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F821SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009595
74F821

Unit Loading/Fan Out

Pin Names

Data Inputs Output Enable 3-STATE Input Clock Input 3-STATE Outputs

Functional Description

The 74F821 consists of ten D-type edge-triggered flipflops. This device has 3-STATE true outputs for bus systems organized in a broadside pinning. The buffered Clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the content of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Logic Diagram

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA
20 µA/−0.6 mA
150/40 mA/24 mA 20 mA

Function Table

Inputs

Internal Output

OE CP D

Function

H X NC

Z Hold

X L H L H

NC H L H L

Z Hold Z Load Z Load L Data Available H Data Available

L H X NC

NC No Change in Data

L X NC

NC No Change in Data

L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial
= High Impedance = LOW-to-HIGH Transition NC = No Change

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F821

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

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Datasheet ID: 74F821SCX 513373