74F675ASC

74F675ASC Datasheet

74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register

Part	Datasheet
74F675ASC	74F675ASC (pdf)

Related Parts	Information
74F675APC	74F675APC
74F675ASCX	74F675ASCX
74F675ASPC	74F675ASPC

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74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register The 74F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer words. By means of a separate clock, the contents of the shift register are transferred to the storage register. The contents of the storage register can also be loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel loading. s Serial-to-parallel converter s 16-Bit serial I/O shift register s 16-Bit parallel out storage register s Recirculating parallel transfer s Expandable for longer words s Slim 24 lead package s 74F675A version prevents false clocking through CS or R/W inputs Ordering Code: Order Number Package Number Package Description 74F675ASC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F675APC N24A 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-011, Wide 74F675ASPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram 2000 Fairchild Semiconductor Corporation DS009587 74F675A Unit Loading/Fan Out Pin Names SI CS SHCP STCP R/W SO Serial Data Input Chip Select Input Active LOW Shift Clock Pulse Input Active Falling Edge Store Clock Pulse Input Active Rising Edge Read/Write Input Serial Data Output Parallel Data Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA Functional Description The 16-Bit shift register operates in one of four modes, as determined by the signals applied to the Chip Select CS , Read/Write R/W and Store Clock Pulse STCP input. State changes are indicated by the falling edge of the Shift Clock Pulse SHCP . In the Shift Right mode, data enters D0 from the Serial Input SI pin and exits from Q15 via the Serial Data Output SO pin. In the Parallel Load mode, data from the storage register outputs enter the shift register and serial shifting is inhibited. The storage register is in the Hold mode when either CS or R/W is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register on the rising edge of STCP. To prevent false clocking of the shift register, SHCP should be in the LOW state during a LOW-to-HIGH transition of CS. To prevent false clocking of the storage register, STCP should be LOW during a HIGH-to-LOW transition of CS if R/W is LOW, and should also be LOW during a HIGH-to-LOW transition of R/W if CS is LOW. Shift Register Operations Table Control Inputs Operating CS R/W SHCP STCP Mode X Hold X Shift Right L Shift Right H Parallel Load, No Shifting Logic Diagram Storage Register Operations Table Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = HIGH-to-LOW Transition = LOW-to-HIGH Transition Operating STCP X Mode Hold Parallel Load Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F675A Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2

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74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register

The 74F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer words. By means of a separate clock, the contents of the shift register are transferred to the storage register. The contents of the storage register can also be loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel loading.
s Serial-to-parallel converter s 16-Bit serial I/O shift register s 16-Bit parallel out storage register s Recirculating parallel transfer s Expandable for longer words s Slim 24 lead package s 74F675A version prevents false clocking through

CS or R/W inputs
Ordering Code:

Order Number Package Number

Package Description
74F675ASC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F675APC

N24A
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-011, Wide
74F675ASPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram
2000 Fairchild Semiconductor Corporation DS009587
74F675A

Unit Loading/Fan Out

Pin Names

SI CS SHCP STCP R/W SO

Serial Data Input Chip Select Input Active LOW Shift Clock Pulse Input Active Falling Edge Store Clock Pulse Input Active Rising Edge Read/Write Input Serial Data Output Parallel Data Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

The 16-Bit shift register operates in one of four modes, as determined by the signals applied to the Chip Select CS , Read/Write R/W and Store Clock Pulse STCP input. State changes are indicated by the falling edge of the Shift Clock Pulse SHCP . In the Shift Right mode, data enters D0 from the Serial Input SI pin and exits from Q15 via the Serial Data Output SO pin. In the Parallel Load mode, data from the storage register outputs enter the shift register and serial shifting is inhibited.

The storage register is in the Hold mode when either CS or R/W is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register on the rising edge of STCP.

To prevent false clocking of the shift register, SHCP should be in the LOW state during a LOW-to-HIGH transition of CS. To prevent false clocking of the storage register, STCP should be LOW during a HIGH-to-LOW transition of CS if R/W is LOW, and should also be LOW during a HIGH-to-LOW transition of R/W if CS is LOW.

Shift Register Operations Table

Control Inputs

Operating

CS R/W SHCP STCP

Mode

X Hold X Shift Right L Shift Right H Parallel Load,

No Shifting

Logic Diagram

Storage Register Operations Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= HIGH-to-LOW Transition = LOW-to-HIGH Transition

Operating

STCP X

Mode Hold Parallel Load

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F675A

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2

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Datasheet ID: 74F675ASC 513367