74F652SC

74F652SC Datasheet

74F652 Transceivers/Registers

Part	Datasheet
74F652SC	74F652SC (pdf)

Related Parts	Information
74F652SPC	74F652SPC
74F652SCX	74F652SCX

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74F652 Transceivers/Registers 74F652 Transceivers/Registers These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins OEAB, OEBA are provided to control the transceiver function. s Independent registers for A and B buses s Multiplexed real-time and stored data s 74F652 non-inverting data path Ordering Code: Order Number Package Number Package Description 74F652SC Note 1 M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F652SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Note 1 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2004 Fairchild Semiconductor Corporation DS009581 74F652 Unit Loading/Fan Out Pin Names CPAB, CPBA SAB, SBA OEAB, OEBA A and B Inputs/ 3-STATE Outputs Clock Inputs Select Inputs Output Enable Inputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −12 mA/64 mA 48 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA Function Table Inputs Inputs/Outputs Note 2 OEAB OEBA CPAB CPBA SAB SBA A0 thru A7 B0 thru B7 Operating Mode L X H L H or L H or L or L H or L X Input Input Isolation Store A and B Data X Input Not Specified Store A, Hold B X Input Output Store A in Both Registers X Not Specified Input Hold A, Store B X Output Input Store B in Both Registers X L Output Input Real-Time B Data to A Bus X H or L X H Store B Data to A Bus X L X Input Output

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74F652 Transceivers/Registers
74F652 Transceivers/Registers

These devices consist of bus transceiver circuits with D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins OEAB, OEBA are provided to control the transceiver function.
s Independent registers for A and B buses s Multiplexed real-time and stored data s 74F652 non-inverting data path
Ordering Code:

Order Number Package Number

Package Description
74F652SC Note 1

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F652SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Note 1 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2004 Fairchild Semiconductor Corporation DS009581
74F652

Unit Loading/Fan Out

Pin Names

CPAB, CPBA SAB, SBA OEAB, OEBA

A and B Inputs/ 3-STATE Outputs Clock Inputs Select Inputs Output Enable Inputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −12 mA/64 mA 48 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA

Function Table

Inputs

Inputs/Outputs Note 2

OEAB OEBA CPAB CPBA SAB SBA A0 thru A7 B0 thru B7

Operating Mode

L X H L

H or L H or L
or L H or L

X Input

Input

Isolation

Store A and B Data

X Input

Not Specified Store A, Hold B

X Input

Output

Store A in Both Registers

X Not Specified Input

Hold A, Store B

X Output

Input

Store B in Both Registers

X L Output

Input

Real-Time B Data to A Bus

X H or L X H

Store B Data to A Bus

X L X Input

Output

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Datasheet ID: 74F652SC 513364