74F646BSPC

74F646BSPC Datasheet

74F646<br>• 74F646B<br>• 74F648 Octal Transceiver/Register with 3-STATE Outputs

Part	Datasheet
74F646BSPC	74F646BSPC (pdf)

Related Parts	Information
74F646BSC	74F646BSC

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74F646 • 74F646B • 74F648 Octal Transceiver/Register with 3-STATE Outputs 74F646 • 74F646B • 74F648 Octal Transceiver/Register with 3-STATE Outputs These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control G and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time transparent mode data. The direction control determines which bus will receive data when the enable control G is Active LOW. In the isolation mode control G HIGH , A data may be stored in the B register and/or B data may be stored in the A register. s Independent registers for A and B buses s Multiplexed real-time and stored data s 74F648 has inverting data paths s 74F646/74F646B have non-inverting data paths s 74F646B is a faster version of the 74F646 s 3-STATE outputs s 300 mil slim DIP Ordering Code: Order Number Package Number Package Description 74F646SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F646MSA MSA24 24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74F646SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74F646BSC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F646BSPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74F648SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F648SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2000 Fairchild Semiconductor Corporation DS009580 74F646 • 74F646B • 74F648 Logic Symbols 74F646/74F646B IEEE/IEC 74F646/74F646B 74F648 IEEE/IEC 74F648 Connection Diagrams 74F646/74F646B 74F648 74F646 • 74F646B • 74F648 Unit Loading/Fan Out Pin Names CPAB, CPBA SAB, SBA G DIR Data Register A Inputs/ 3-STATE Outputs Data Register B Inputs/ 3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Input Direction Control Input U.L. HIGH/LOW 80 Input IIH/IIL Output IOH/IOL 70 µA/−650 µA −12 mA/64 mA 48 mA 70 µA/−650 µA −12 mA/64 mA 48 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA Function Table Inputs Data I/O Note 1 G DIR CPAB CPBA SAB SBA Function H or L H or L Isolation Input Clock An Data into A Register Clock Bn Data into B Register An to Time Transparent Mode Input Output Clock An Data into A Register H or L X A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn X H or L X H = HIGH Voltage Level L = LOW Voltage Level = Irrelevant = LOW-to-HIGH Transition Bn to Time Transparent Mode L Output Input Clock Bn Data into B Register B Register to An Stored Mode Clock Bn Data into B Register and Output to An Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs. 74F646 • 74F646B • 74F648 Logic Diagrams

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74F646
• 74F646B
• 74F648 Octal Transceiver/Register with 3-STATE Outputs
74F646
• 74F646B
• 74F648 Octal Transceiver/Register with 3-STATE Outputs

These devices consist of bus transceiver circuits with 3-STATE, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. Control G and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or the B register or in both. The select controls can multiplex stored and real-time transparent mode data. The direction control determines which bus will receive data when the enable control G is Active LOW. In the isolation mode control G HIGH , A data may be stored in the B register and/or B data may be stored in the A register.
s Independent registers for A and B buses s Multiplexed real-time and stored data s 74F648 has inverting data paths s 74F646/74F646B have non-inverting data paths s 74F646B is a faster version of the 74F646 s 3-STATE outputs s 300 mil slim DIP
Ordering Code:

Order Number Package Number

Package Description
74F646SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F646MSA

MSA24
24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74F646SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74F646BSC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F646BSPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74F648SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F648SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2000 Fairchild Semiconductor Corporation DS009580
74F646
• 74F646B
• 74F648

Logic Symbols
74F646/74F646B

IEEE/IEC 74F646/74F646B
74F648

IEEE/IEC 74F648

Connection Diagrams
74F646/74F646B
74F648
74F646
• 74F646B
• 74F648

Unit Loading/Fan Out

Pin Names

CPAB, CPBA SAB, SBA G DIR

Data Register A Inputs/ 3-STATE Outputs Data Register B Inputs/ 3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Input Direction Control Input

U.L. HIGH/LOW 80

Input IIH/IIL Output IOH/IOL 70 µA/−650 µA −12 mA/64 mA 48 mA 70 µA/−650 µA −12 mA/64 mA 48 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA

Function Table

Inputs

Data I/O Note 1

G DIR CPAB CPBA SAB SBA

Function

H or L H or L

Isolation

Input Clock An Data into A Register

Clock Bn Data into B Register

An to Time Transparent Mode

Input Output Clock An Data into A Register

H or L X

A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn

X H or L X

H = HIGH Voltage Level L = LOW Voltage Level
= Irrelevant = LOW-to-HIGH Transition

Bn to Time Transparent Mode

L Output Input Clock Bn Data into B Register

B Register to An Stored Mode

Clock Bn Data into B Register and Output to An

Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.
74F646
• 74F646B
• 74F648

Logic Diagrams

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Datasheet ID: 74F646BSPC 513363