74F579PC

74F579PC Datasheet

74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs

Part	Datasheet
74F579PC	74F579PC (pdf)

Related Parts	Information
74F579SJ	74F579SJ
74F579SC	74F579SC
74F579SCX	74F579SCX

PDF Datasheet Preview
74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs 74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs The 74F579 is a fully synchronous 8-stage up/down counter with multiplexed 3-STATE I/O ports for bus-oriented applications. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock. s Multiplexed 3-STATE I/O ports s Built-in lookahead carry capability s Count frequency 100 MHz typical s Supply current 75 mA typical s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number Package Number Package Description 74F579SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F579SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F579PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code. Logic Symbol Connection Diagram 2000 Fairchild Semiconductor Corporation DS009568 74F579 Unit Loading/Fan Out Pin Names PE U/D MR SR CEP CET CS OE CP TC Data Inputs or 3-STATE Outputs Parallel Enable Input Active LOW Up-Down Count Control Input Master Reset Input Active LOW Synchronous Reset Input Active LOW Count Enable Parallel Input Active LOW Count Enable Trickle Input Active LOW Chip Select Input Active LOW Output Enable Input Active LOW Clock Pulse Input Active Rising Edge Terminal Count Output Active LOW U.L. HIGH/LOW 75/15 Input IIH/IIL Output IOH/IOL 70 µA/−0.2 mA −3 mA/24 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA −1 mA/5 mA Function Table MR SR CS PE CEP CET U/D OE CP Function X H X I/Oa to I/Oh in High Z PE Disabled X L H X H X I/Oa to I/Oh in High Z X L H X L X Flip-Flop Outputs Appear on I/O Lines XX LL Not LL Not LL Not LL Not LL X H X L Asynchronous Reset for all Flip-Flops Synchronous Reset for all Flip-Flops Parallel Load all Flip-Flops Hold TC Held HIGH Count Up Count Down H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW to HIGH Clock Transition Not LL = CS and PE should never both be LOW voltage level at the same time. 74F579 Logic Diagrams Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. VCC = Pin 16 GND = Pin 6 = Pin Numbers Detail A 74F579 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA

PDF Datasheet Preview

74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs

The 74F579 is a fully synchronous 8-stage up/down counter with multiplexed 3-STATE I/O ports for bus-oriented applications. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock.
s Multiplexed 3-STATE I/O ports s Built-in lookahead carry capability s Count frequency 100 MHz typical s Supply current 75 mA typical s Guaranteed 4000V minimum ESD protection
Ordering Code:

Order Number Package Number

Package Description
74F579SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F579SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F579PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” tot he ordering code.

Logic Symbol

Connection Diagram
2000 Fairchild Semiconductor Corporation DS009568
74F579

Unit Loading/Fan Out

Pin Names

PE U/D MR SR CEP CET CS OE CP TC

Data Inputs or 3-STATE Outputs Parallel Enable Input Active LOW Up-Down Count Control Input Master Reset Input Active LOW Synchronous Reset Input Active LOW Count Enable Parallel Input Active LOW Count Enable Trickle Input Active LOW Chip Select Input Active LOW Output Enable Input Active LOW Clock Pulse Input Active Rising Edge Terminal Count Output Active LOW

U.L. HIGH/LOW
75/15

Input IIH/IIL Output IOH/IOL 70 µA/−0.2 mA −3 mA/24 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA 5 µA/−0.2 mA
−1 mA/5 mA

Function Table

MR SR CS PE CEP CET U/D OE CP

Function

X H X I/Oa to I/Oh in High Z PE Disabled X L H X H X I/Oa to I/Oh in High Z X L H X L X Flip-Flop Outputs Appear on I/O Lines

XX LL Not LL Not LL Not LL Not LL

X H X L

Asynchronous Reset for all Flip-Flops Synchronous Reset for all Flip-Flops Parallel Load all Flip-Flops Hold TC Held HIGH Count Up Count Down

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW to HIGH Clock Transition Not LL = CS and PE should never both be LOW voltage level at the same time.
74F579

Logic Diagrams

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

VCC = Pin 16

GND = Pin 6
= Pin Numbers

Detail A
74F579

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

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Datasheet ID: 74F579PC 513356