74F574PC

74F574PC Datasheet

74F574 Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74F574PC	74F574PC (pdf)

Related Parts	Information
74F574SJX	74F574SJX
74F574SJ	74F574SJ
74F574SC	74F574SC
74F574SCX	74F574SCX

PDF Datasheet Preview
74F574 Octal D-Type Flip-Flop with 3-STATE Outputs 74F574 Octal D-Type Flip-Flop with 3-STATE Outputs The 74F574 is a high-speed, low power octal flip-flop with a buffered common Clock CP and a buffered common Output Enable OE . The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock CP transition. This device is functionally identical to the 74F374 except for the pinouts. s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74F374 s 3-STATE outputs for bus-oriented applications Ordering Code: Order Number Package Number Package Description 74F574SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F574SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F574PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009567 74F574 Unit Loading/Fan Out Pin Names CP OE Data Inputs Clock Pulse Input Active LOW 3-STATE Output Enable Input Active LOW 3-STATE Outputs U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA Functional Description The 74F574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops. Function Table Inputs Internal Outputs OE CP D Function Z Hold H L H L H NC L H L H Z Hold Z Load Z Load L Data Available H Data Available NC No Change in Data L H NC NC No Change in Data H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F574 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V

PDF Datasheet Preview

74F574 Octal D-Type Flip-Flop with 3-STATE Outputs
74F574 Octal D-Type Flip-Flop with 3-STATE Outputs

The 74F574 is a high-speed, low power octal flip-flop with a buffered common Clock CP and a buffered common Output Enable OE . The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH Clock CP transition.

This device is functionally identical to the 74F374 except for the pinouts.
s Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
s Useful as input or output port for microprocessors s Functionally identical to 74F374 s 3-STATE outputs for bus-oriented applications
Ordering Code:

Order Number Package Number

Package Description
74F574SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F574SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F574PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009567
74F574

Unit Loading/Fan Out

Pin Names

CP OE

Data Inputs Clock Pulse Input Active LOW 3-STATE Output Enable Input Active LOW 3-STATE Outputs

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA

Functional Description

The 74F574 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flipflops.

Function Table

Inputs

Internal Outputs

OE CP D

Function

Z Hold

H L H L H

NC L H L H

Z Hold Z Load Z Load L Data Available H Data Available

NC No Change in Data

L H NC

NC No Change in Data

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= High Impedance = LOW-to-HIGH Transition NC = No Change

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F574

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

More datasheets: CQX16 | 3672 | 43-00095 | 43-00097 | APDS-9101-L21 | CYV15G0104EQ-LXC | 10921S | 74F574SJX | 74F574SJ | 74F574SC

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Datasheet ID: 74F574PC 513355