74F538PC

74F538PC Datasheet

74F538 1-of-8 Decoder with 3-STATE Outputs

Part	Datasheet
74F538PC	74F538PC (pdf)

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74F538 1-of-8 Decoder with 3-STATE Outputs 74F538 1-of-8 Decoder with 3-STATE Outputs The 74F538 decoder/demultiplexer accepts three Address input signals and decodes them to select one of eight mutually exclusive outputs. A polarity control input P determines whether the outputs are active LOW or active HIGH. A HIGH Signal on either of the active LOW Output Enable OE inputs forces all outputs to the high impedance state. Two active HIGH and two active LOW input enables are available for easy expansion to 1-of 32 decoding with four packages, or for data demultiplexing to 1-of-8 or 1-of-16 destinations. s Output polarity control s Data demultiplexing capability s Multiple enables for expansion s 3-STATE outputs Ordering Code: Order Number Package Number Package Description 74F538SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F538PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2004 Fairchild Semiconductor Corporation DS009551 74F538 Unit Loading/Fan Out Pin Names E1, E2 E3, E4 P OE1, OE2 Address Inputs Enable Inputs Active LOW Enable Inputs Active HIGH Polarity Control Input Output Enable Inputs Active LOW 3-STATE Outputs U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA Truth Table Function Inputs Outputs OE1 OE2 E1 E2 E3 E4 A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7 High Impedance Disable L XXLXXXX Outputs Equal P Input L XXXLXXX Active HIGH L LHHL L LHL L Output L LHHL LHLHL L L LHHLHL L LHL L L LHHLHHL L LHL L L LHHHL L LH L L LHHHLHL L LHL L L LHHHH L LHL Active LOW L LHHL L Output L LHHL L LHHLH LHH L LHHHL LHHHHLHHH L LHH L LHHHH

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74F538 1-of-8 Decoder with 3-STATE Outputs
74F538 1-of-8 Decoder with 3-STATE Outputs

The 74F538 decoder/demultiplexer accepts three Address input signals and decodes them to select one of eight mutually exclusive outputs. A polarity control input P determines whether the outputs are active LOW or active HIGH. A HIGH Signal on either of the active LOW Output Enable OE inputs forces all outputs to the high impedance state. Two active HIGH and two active LOW input enables are available for easy expansion to 1-of 32 decoding with four packages, or for data demultiplexing to 1-of-8 or 1-of-16 destinations.
s Output polarity control s Data demultiplexing capability s Multiple enables for expansion s 3-STATE outputs
Ordering Code:

Order Number Package Number

Package Description
74F538SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F538PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2004 Fairchild Semiconductor Corporation DS009551
74F538

Unit Loading/Fan Out

Pin Names

E1, E2 E3, E4 P OE1, OE2

Address Inputs Enable Inputs Active LOW Enable Inputs Active HIGH Polarity Control Input Output Enable Inputs Active LOW 3-STATE Outputs

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA

Truth Table

Function

Inputs

Outputs

OE1 OE2 E1 E2 E3 E4 A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7

High

Impedance

Disable

L XXLXXXX

Outputs Equal P Input

L XXXLXXX

Active HIGH

L LHHL L LHL L

Output

L LHHL LHLHL L

L LHHLHL L LHL L

L LHHLHHL L LHL L

L LHHHL L LH L

L LHHHLHL L LHL L

L LHHHH L LHL

Active LOW

L LHHL L

Output

L LHHL

L LHHLH LHH

L LHHHL LHHHHLHHH

L LHH

L LHHHH

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Datasheet ID: 74F538PC 513344