74ACTQ16373SSCX

74ACTQ16373SSCX Datasheet

74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs

Part	Datasheet
74ACTQ16373SSCX	74ACTQ16373SSCX (pdf)

Related Parts	Information
74ACTQ16373SSC	74ACTQ16373SSC
74ACTQ16373MTDX	74ACTQ16373MTDX
74ACTQ16373MTD	74ACTQ16373MTD

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74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs 74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs The ACTQ16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable LE is HIGH. When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in high Z state. The ACTQ16373 utilizes Fairchild’s Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control for superior performance. s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte s 16-bit version of the ACTQ373 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output Loading specs for both 50 pF and 250 pF loads Ordering Code: Order Number Package Number Package Description 74ACTQ16373SSC MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74ACTQ16373MTD MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names OEn LEn Output Enable Input Active LOW Latch Enable Input Inputs Outputs Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS010934 74ACTQ16373 Functional Description The ACTQ16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable OEn input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagrams Truth Tables Inputs X L H X Outputs Z L H Previous Inputs Outputs Previous H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Previous output prior to HIGH-to-LOW transition of LE 74ACTQ16373 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI VCC 0.5V DC Output Diode Current IOK VO VCC 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature mA to VCC 0.5V mA Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 'V/'t 4.5V to 5.5V 0V to VCC 0V to VCC to 125 mV/ns VIN from 0.8V to 2.0V VCC 4.5V, 5.5V Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications. DC Electrical Characteristics Parameter to Units Conditions Guaranteed Limits Minimum HIGH

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74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs
74ACTQ16373 16-Bit Transparent Latch with 3-STATE Outputs

The ACTQ16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable LE is HIGH. When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in high Z state. The ACTQ16373 utilizes Fairchild’s Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control for superior performance.
s Utilizes Fairchild FACT Quiet Series technology s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin output skew s Separate control logic for each byte s 16-bit version of the ACTQ373 s Outputs source/sink 24 mA s Additional specs for Multiple Output Switching s Output Loading specs for both 50 pF and 250 pF loads
Ordering Code:

Order Number Package Number

Package Description
74ACTQ16373SSC

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74ACTQ16373MTD

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names

OEn LEn

Output Enable Input Active LOW Latch Enable Input Inputs Outputs

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS010934
74ACTQ16373

Functional Description

The ACTQ16373 contains sixteen D-type latches with 3STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3STATE standard outputs are controlled by the Output Enable OEn input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagrams

Truth Tables

Inputs

X L H X

Outputs

Z L H Previous

Inputs

Outputs

Previous

H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Previous output prior to HIGH-to-LOW transition of LE
74ACTQ16373

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI VCC 0.5V DC Output Diode Current IOK VO VCC 0.5V DC Output Voltage VO DC Output Source/Sink Current IO DC VCC or Ground Current per Output Pin

Junction Temperature

Storage Temperature
mA to VCC 0.5V mA

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 'V/'t
4.5V to 5.5V
0V to VCC 0V to VCC to 125 mV/ns

VIN from 0.8V to 2.0V

VCC 4.5V, 5.5V

Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications.

DC Electrical Characteristics

Parameter
to Units

Conditions

Guaranteed Limits

Minimum HIGH

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Datasheet ID: 74ACTQ16373SSCX 513200