74F533SJ

74F533SJ Datasheet

74F533 Octal Transparent Latch with 3-STATE Outputs

Part	Datasheet
74F533SJ	74F533SJ (pdf)

Related Parts	Information
74F533SC	74F533SC
74F533SCX	74F533SCX
74F533PC	74F533PC

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74F533 Octal Transparent Latch with 3-STATE Outputs 74F533 Octal Transparent Latch with 3-STATE Outputs The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state. The 74F533 is the same as the 74F373, except that the outputs are inverted. s Eight latches in a single package s 3-STATE outputs for bus interfacing s Inverted version of the 74F373 Ordering Code: Order Number Package Number Package Description 74F533SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F533SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F533PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009548 74F533 Unit Loading/Fan Out Pin Names LE OE Data Inputs Latch Enable Input Active HIGH Output Enable Input Active LOW Complementary 3-STATE Outputs U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA Function Table Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Output O L H O0 Z Functional Description The 74F533 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F533 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage Note 2 −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max

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74F533 Octal Transparent Latch with 3-STATE Outputs
74F533 Octal Transparent Latch with 3-STATE Outputs

The 74F533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state. The 74F533 is the same as the 74F373, except that the outputs are inverted.
s Eight latches in a single package s 3-STATE outputs for bus interfacing s Inverted version of the 74F373
Ordering Code:

Order Number Package Number

Package Description
74F533SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F533SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F533PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009548
74F533

Unit Loading/Fan Out

Pin Names

LE OE

Data Inputs Latch Enable Input Active HIGH Output Enable Input Active LOW Complementary 3-STATE Outputs

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA

Function Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Output

O L H O0 Z

Functional Description

The 74F533 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F533

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin
−0.5V to +7.0V

Input Voltage Note 2
−0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max

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Datasheet ID: 74F533SJ 513341