74F402PC

74F402PC Datasheet

74F402 Serial Data Polynomial Generator/Checker

Part	Datasheet
74F402PC	74F402PC (pdf)

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74F402 Serial Data Polynomial Generator/Checker 74F402 Serial Data Polynomial Generator/Checker The 74F402 expandable Serial Data Polynomial generator/ checker is an expandable version of the 74F401. It provides an advanced tool for the implementation of the most widely used error detection scheme in serial digital handling systems. A 4-bit control input selects one-of-six generator polynomials. The list of polynomials includes CRC16, CRC-CCITT and as well as three other standard polynomials 56th order, 48th order, 32nd order . Individual clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. The CWG Control input inhibits feedback during check word transmission. The 74F402 is compatible with devices and with all TTL families. s Guaranteed 30 MHz data rate s Six selectable polynomials s Other polynomials available s Separate preset and clear controls s Expandable s Automatic right justification s Error output open collector s Typical applications Floppy and other disk storage sys- tems Digital cassette and cartridge systems Data communication systems Ordering Code: Order Number Package Number Package Description 74F402PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Logic Symbol Connection Diagram is a registered trademark of Fairchild Semiconductor Corporation. is a registered trademark of Xerox Corporation. 1999 Fairchild Semiconductor Corporation DS009535 74F402 Unit Loading/Fan Out Pin Names CWG D/CW D ER RO CP SEI RFB MR P Note 1 Open Collector Polynomial Select Inputs Check Word Generate Input Serial Data/Check Word Data Input Error Output Register Output Clock Pulse Serial Expansion Input Register Feedback Master Reset Preset U.L. HIGH/LOW Note 1 Input IIH/IIL Output IOH/IOL 20 µA/−0.4 mA 20 µA/−0.4 mA −2 mA /8 mA 4 mA 20 µA/−0.4 mA Note 1 /16 mA 8 mA mA −2 mA /8 mA 4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA Functional Description The 74F402 Serial Data Polynomial Generator/Checker is an expandable 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream message polynomial is divided by a selected polynomial. This division results in a remainder or residue which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F402 implements the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1, S2 and S3. The 74F402 consists of a 16-bit register, a Read Only Memory ROM and associated control circuitry as shown in the Block Diagram. The polynomial control code presented at inputs S0, S1, S2 and S3 is decoded by the ROM, selecting the desired polynomial or part of a polynomial by establishing shift mode operation on the register with Exclusive OR XOR gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data Inputs D , using the LOW-to-HIGH transition of the Clock Input CP . This data is gated with the most significant Register Output RO via the Register Feedback Input RFB , and controls the XOR gates. The Check Word Gen- erate CWG must be held HIGH while the data is being entered. After the last data bit is entered, the CWG is brought LOW and the check bits are shifted out of the register s and appended to the data bits no external gating is needed . To check an incoming message for errors, both the data and check bits are entered through the D Input with the CWG Input held HIGH. The Error Output becomes valid after the last check bit has been entered into the ’F402 by a LOW-to-HIGH transition of CP, with the exception of the Ethernet polynomial see Applications paragraph . If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output ER is HIGH. If a detectable error has occurred, ER is LOW. ER remains valid until the next LOWto-HIGH transition of CP or until the device has been preset or reset. A HIGH on the Master Reset Input MR asynchronously clears the entire register. A LOW on the Preset Input P asynchronously sets the entire register with the exception of: The Ethernet residue selection, in which the registers containing the non-zero residue are cleared; The 56th order polynomial, in which the 8 least significant register bits of the least significant device are cleared and, Register S = 0, in which all bits are cleared. 74F402 Hex S3 Select Code Block Diagram TABLE Polynomial S0 Remarks X32+X26+X23+X22+X16+ Ethernet H X12+X11+X10+X8+X7+X5+X4+X2+X+1 Polynomial X32+X31+X27+X26+X25+X19+X16+

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74F402 Serial Data Polynomial Generator/Checker
74F402 Serial Data Polynomial Generator/Checker

The 74F402 expandable Serial Data Polynomial generator/ checker is an expandable version of the 74F401. It provides an advanced tool for the implementation of the most widely used error detection scheme in serial digital handling systems. A 4-bit control input selects one-of-six generator polynomials. The list of polynomials includes CRC16, CRC-CCITT and as well as three other standard polynomials 56th order, 48th order, 32nd order . Individual clear and preset inputs are provided for floppy disk and other applications. The Error output indicates whether or not a transmission error has occurred. The CWG Control input inhibits feedback during check word transmission. The 74F402 is compatible with devices and with all TTL families.
s Guaranteed 30 MHz data rate s Six selectable polynomials s Other polynomials available s Separate preset and clear controls s Expandable s Automatic right justification s Error output open collector s Typical applications Floppy and other disk storage sys-
tems Digital cassette and cartridge systems Data communication systems
Ordering Code:

Order Number Package Number

Package Description
74F402PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Logic Symbol

Connection Diagram
is a registered trademark of Fairchild Semiconductor Corporation. is a registered trademark of Xerox Corporation.
1999 Fairchild Semiconductor Corporation DS009535
74F402

Unit Loading/Fan Out

Pin Names

CWG D/CW D ER RO CP SEI RFB MR P

Note 1 Open Collector

Polynomial Select Inputs Check Word Generate Input Serial Data/Check Word Data Input Error Output Register Output Clock Pulse Serial Expansion Input Register Feedback Master Reset Preset

U.L. HIGH/LOW

Note 1

Input IIH/IIL Output IOH/IOL 20 µA/−0.4 mA 20 µA/−0.4 mA −2 mA /8 mA 4 mA 20 µA/−0.4 mA Note 1 /16 mA 8 mA
mA −2 mA /8 mA 4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA 20 µA/−0.4 mA

Functional Description

The 74F402 Serial Data Polynomial Generator/Checker is an expandable 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream message polynomial is divided by a selected polynomial. This division results in a remainder or residue which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F402 implements the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1, S2 and S3.

The 74F402 consists of a 16-bit register, a Read Only Memory ROM and associated control circuitry as shown in the Block Diagram. The polynomial control code presented at inputs S0, S1, S2 and S3 is decoded by the ROM, selecting the desired polynomial or part of a polynomial by establishing shift mode operation on the register with Exclusive OR XOR gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data Inputs D , using the LOW-to-HIGH transition of the Clock Input CP . This data is gated with the most significant Register Output RO via the Register Feedback Input RFB , and controls the XOR gates. The Check Word Gen-
erate CWG must be held HIGH while the data is being entered. After the last data bit is entered, the CWG is brought LOW and the check bits are shifted out of the register s and appended to the data bits no external gating is needed .

To check an incoming message for errors, both the data and check bits are entered through the D Input with the CWG Input held HIGH. The Error Output becomes valid after the last check bit has been entered into the ’F402 by a LOW-to-HIGH transition of CP, with the exception of the Ethernet polynomial see Applications paragraph . If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output ER is HIGH. If a detectable error has occurred, ER is LOW. ER remains valid until the next LOWto-HIGH transition of CP or until the device has been preset or reset.

A HIGH on the Master Reset Input MR asynchronously clears the entire register. A LOW on the Preset Input P asynchronously sets the entire register with the exception of:

The Ethernet residue selection, in which the registers containing the non-zero residue are cleared;

The 56th order polynomial, in which the 8 least significant register bits of the least significant device are cleared and,

Register S = 0, in which all bits are cleared.
74F402

Hex S3

Select Code

Block Diagram

TABLE

Polynomial S0

Remarks

X32+X26+X23+X22+X16+

Ethernet

H X12+X11+X10+X8+X7+X5+X4+X2+X+1

Polynomial

X32+X31+X27+X26+X25+X19+X16+

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Datasheet ID: 74F402PC 513335