74F398PC

74F398PC Datasheet

74F398<br>• 74F399 Quad 2-Port Register

Part	Datasheet
74F398PC	74F398PC (pdf)

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74F398 • 74F399 Quad 2-Port Register 74F398 • 74F399 Quad 2-Port Register The 74F398 and 74F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flops on the rising edge of the clock. The 74F399 is the 16-pin version of the 74F398, with only the Q outputs of the flip-flops available. s Select inputs from two data sources s Fully positive edge-triggered operation s Both true and complement Ordering Code: Order Number Package Number Package Description 74F398SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F398PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74F399SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F399SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F399PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams 74F398 74F399 2000 Fairchild Semiconductor Corporation DS009533 74F398 • 74F399 Logic Symbols 74F398 74F398 74F399 74F399 IEEE/IEC Unit Loading/Fan Out Pin Names Common Select Input Clock Pulse Input Active Rising Edge Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs Register Complementary Outputs 74F398 U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA 74F398 • 74F399 Functional Description The 74F398 and 74F399 are high-speed quad 2-port registers. They select four bits of data from either of two sources Ports under control of a common Select input S . The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input CP . The 4-bit D-type output register is fully edgetriggered. The Data inputs I0x, I1x and Select input S must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. The 74F398 has both Q and Q outputs. Logic Diagram Function Table Inputs Outputs Note 1 H = HIGH Voltage Level L = LOW Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X = Immaterial Note 1 74F398 only *F398 Only Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F398 • 74F399 Absolute Maximum Ratings Note 2 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 3 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 3

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74F398
• 74F399 Quad 2-Port Register
74F398
• 74F399 Quad 2-Port Register

The 74F398 and 74F399 are the logical equivalents of a quad 2-input multiplexer feeding into four edge-triggered flip-flops. A common Select input determines which of the two 4-bit words is accepted. The selected data enters the flip-flops on the rising edge of the clock. The 74F399 is the 16-pin version of the 74F398, with only the Q outputs of the flip-flops available.
s Select inputs from two data sources s Fully positive edge-triggered operation s Both true and complement
Ordering Code:

Order Number Package Number

Package Description
74F398SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F398PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74F399SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F399SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F399PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams
74F398
74F399
2000 Fairchild Semiconductor Corporation DS009533
74F398
• 74F399

Logic Symbols
74F398
74F398
74F399
74F399

IEEE/IEC

Unit Loading/Fan Out

Pin Names

Common Select Input Clock Pulse Input Active Rising Edge Data Inputs from Source 0 Data Inputs from Source 1 Register True Outputs Register Complementary Outputs 74F398

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA
74F398
• 74F399

Functional Description

The 74F398 and 74F399 are high-speed quad 2-port registers. They select four bits of data from either of two sources Ports under control of a common Select input S . The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input CP . The 4-bit D-type output register is fully edgetriggered. The Data inputs I0x, I1x and Select input S must be stable only a setup time prior to and hold time after the LOW-to-HIGH transition of the Clock input for predictable operation. The 74F398 has both Q and Q outputs.

Logic Diagram

Function Table

Inputs

Outputs

Note 1

H = HIGH Voltage Level L = LOW Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH
clock transition I = LOW Voltage Level one setup time prior to the LOW-to-HIGH
clock transition X = Immaterial

Note 1 74F398 only
*F398 Only Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F398
• 74F399

Absolute Maximum Ratings Note 2

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 3
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 3

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Datasheet ID: 74F398PC 513332