74F379PC

74F379PC Datasheet

74F379 Quad Parallel Register with Enable

Part	Datasheet
74F379PC	74F379PC (pdf)

Related Parts	Information
74F379SJ	74F379SJ
74F379SC	74F379SC
74F379SJX	74F379SJX
74F379SCX	74F379SCX

PDF Datasheet Preview
74F379 Quad Parallel Register with Enable 74F379 Quad Parallel Register with Enable The 74F379 is a 4-bit register with buffered common Enable. This device is similar to the 74F175 but features the common Enable rather than common Master Reset. s Edge triggered D-type inputs s Buffered positive edge-triggered clock s Buffered common enable input s True and complement outputs Ordering Code: Order Number Package Number Package Description 74F379SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F379SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F379PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009527 74F379 Unit Loading/Fan Out Pin Names Enable Input Active LOW Data Inputs Clock Pulse Input Active Rising Edge Flip-Flop Outputs Complement Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA Functional Description Truth Table The 74F379 consists of four edge-triggered D-type flipflops with individual D inputs and Q and Q outputs. The Clock CP and Enable E inputs are common to all flipflops. When the E is input HIGH, the register will retain the present data independent of the CP input. The Dn and E inputs can change when the clock is in either state, provided that the recommended setup and hold times are observed. Inputs H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition NC = No Change Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F379 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA ESD Last Passing Voltage Min 4000V

PDF Datasheet Preview

74F379 Quad Parallel Register with Enable
74F379 Quad Parallel Register with Enable

The 74F379 is a 4-bit register with buffered common Enable. This device is similar to the 74F175 but features the common Enable rather than common Master Reset.
s Edge triggered D-type inputs s Buffered positive edge-triggered clock s Buffered common enable input s True and complement outputs
Ordering Code:

Order Number Package Number

Package Description
74F379SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F379SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F379PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009527
74F379

Unit Loading/Fan Out

Pin Names

Enable Input Active LOW Data Inputs Clock Pulse Input Active Rising Edge Flip-Flop Outputs Complement Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL
20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

Truth Table

The 74F379 consists of four edge-triggered D-type flipflops with individual D inputs and Q and Q outputs. The Clock CP and Enable E inputs are common to all flipflops. When the E is input HIGH, the register will retain the present data independent of the CP input. The Dn and E inputs can change when the clock is in either state, provided that the recommended setup and hold times are observed.

Inputs

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Transition NC = No Change

Outputs

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F379

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

ESD Last Passing Voltage Min
4000V

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74F379PC Datasheet file may be downloaded here without warranties.

Datasheet ID: 74F379PC 513328