CS4525-CNZR

CS4525-CNZR Datasheet

CS4525

Part	Datasheet
CS4525-CNZR	CS4525-CNZR (pdf)

Related Parts	Information
CRD4525-Q1	CRD4525-Q1
CS4525-CNZ	CS4525-CNZ

PDF Datasheet Preview
CS4525 30 W Digital Audio Amplifier with Integrated ADC Digital Amplifier Features Fully Integrated Power MOSFETs No Heatsink Required Programmable Power Foldback on Thermal Warning High Efficiency > 100 dB Dynamic Range < THD+N 1 W Configurable Outputs 10% THD+N 1 x 30 W into 4 Ω, Parallel Full-Bridge 2 x 15 W into 8 Ω, Full-Bridge 2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W into 8 Ω, Full-Bridge Built-In Protection with Error Reporting Overcurrent/Undervoltage/Thermal Overload Shutdown Thermal Warning Reporting PWM for Half-Bridge Mode Click-Free Start-Up Programmable Channel Delay for System Noise & Radiated Emissions Management ADC Features Stereo, 24-bit, 48 kHz Conversion Multi-bit Architecture 95 dB Dynamic Range A-wtd -86 dB THD+N Supports 2 Vrms Input with Passive Components System Features Asynchronous 2-Channel Digital Serial Port 32 kHz to 96 kHz Input Sample Rates Operation with On-Chip Oscillator Driver or Applied SYS_CLK at or MHz Integrated Sample Rate Converter SRC Eliminates Clock-Jitter Effects Input Sample Rate Independent Operation Simplifies System Integration Spread Spectrum PWM Modulation Reduces EMI Radiated Energy Low Quiescent Current Features continued on page 2 System Clock Crystal Driver I/O Stereo Analog In Serial Audio Clocks & Data Serial Audio Data I/O Serial Audio Clocks & Data HP Detect/Mute Reset Interrupt or Hardware Configuration Crystal Oscillator Driver Multi-bit ADC Serial Audio Input Port Serial Audio Delay Interface Auxiliary Serial Port Register /Hardware Configuration V to 5 V Audio Processing Parametric EQ High-Pass Bass/Treble Adaptive Loudness Compensation 2-Ch Mixer Bass Mgr Linkwitz-Riley Crossover De-Emphasis Volume Multi-bit Modulator with Integrated Sample Rate Converter Error Protection Please refer to “Ordering Information” on page 97 for complete ordering information. DS726PP2 CS4525 TABLE OF CONTENTS PIN DESCRIPTIONS - SOFTWARE MODE 8 PIN DESCRIPTIONS - HARDWARE MODE 10 Digital I/O Pin Characteristics 12 TYPICAL CONNECTION DIAGRAMS 13 TYPICAL SYSTEM CONFIGURATION DIAGRAMS 15 CHARACTERISTICS AND SPECIFICATIONS 18 APPLICATIONS 26 Software Mode 26 System Clocking 26 SYS_CLK Input Clock Mode 26 Crystal Oscillator Mode 27 Power-Up and Power-Down 28 Recommended Power-Up Sequence 28 Recommended Power-Down Sequence 28 Input Source Selection 29 Digital Sound Processing 29 Pre-Scaler 30 Digital Signal Processing High-Pass Filter 30 Channel Mixer 30 De-Emphasis 31 Tone Control 31 Parametric EQ 33 Adaptive Loudness Compensation 34 Bass Management 35 Volume and Muting Control 36 Peak Signal Limiter 37 Thermal Limiter 39 Thermal Foldback 40 2-Way Crossover & Sensitivity Control 41 Auxiliary Serial Output 43 Serial Audio Delay & Warning Input Port 44 Serial Audio Delay Interface 44 External Warning Input Port 44 Powered PWM Outputs 45 Output Channel Configurations 45 PWM Popguard Transient Control 45 Logic-Level PWM Outputs 46 Recommended PWM_SIG Power-Up Sequence for an External PWM Amplifier 47 Recommended PWM_SIG Power-Down Sequence for an External PWM Amplifier 47 Recommended PWM_SIG Power-Up Sequence for Headphone & Line-Out 48 Recommended PWM_SIG Power-Down Sequence for Headphone & Line-Out 48 PWM_SIG Logic-Level Output Configurations 49 PWM Modulator Configuration 50 PWM Channel Delay 50 PWM AM Frequency Shift 51 Headphone Detection & Hardware Mute Input 51 Interrupt Reporting 53 Automatic Power Stage Shut-Down 53 Hardware Mode 54 System Clocking 54 Power-Up and Power-Down 54 Recommended Power-Up Sequence 54 DS726PP2 CS4525 Recommended Power-Down Sequence 55 Input Source Selection 55 PWM Channel Delay 55 Digital Signal Flow 56 High-Pass Filter 56 Mute Control 56 Warning and Error Reporting 56 Thermal Foldback 57 Automatic Power Stage Shut-Down 58 PWM Modulators and Sample Rate Converters 58 Output Filters 59 Half-Bridge Output Filter 59 Full-Bridge Output Filter Stereo or Parallel 60 Analog Inputs 61 Serial Audio Interfaces 62 Data Format 62 Left-Justified Data Format 62 Right-Justified Data Format 63 Integrated VD Regulator 63 Control Port Description and Timing 64 PCB LAYOUT CONSIDERATIONS 65 Power Supply, Grounding 65 QFN Thermal Pad 65 REGISTER QUICK REFERENCE 66 REGISTER DESCRIPTIONS 69 Clock Configuration Address 01h 69 SYS_CLK Output Enable EnSysClk 69 SYS_CLK Output Divider DivSysClk 69 Clock Frequency ClkFreq[1:0] 69 HP_Detect/Mute Pin Active Logic Level HP/MutePol 70 HP_Detect/Mute Pin Mode HP/Mute 70 Modulator Phase Shifting PhaseShift 70 AM Frequency Shifting FreqShift 70 Input Configuration Address 02h 71 Input Source Selection ADC/SP 71 ADC High-Pass Filter Enable EnAnHPF 71 Serial Port Sample Rate SPRate[1:0] - Read Only 71 Input Serial Port Digital Interface Format DIF [2:0] 71 AUX Port Configuration Address 03h 72 Enable Aux Serial Port EnAuxPort 72 Delay & Warning Port Configuration DlyPortCfg[1:0] 72 Aux/Delay Serial Port Digital Interface Format 72 Aux Serial Port Right Channel Data Select RChDSel[1:0] 72 Aux Serial Port Left Channel Data Select LChDSel[1:0] 73 Output Configuration Address 04h 73 Output Configuration OutputCfg[1:0] 73 PWM Signals Output Data Select PWMDSel[1:0] 73 Channel Delay Settings OutputDly[3:0] 73 Foldback and Ramp Configuration Address 05h 74 Select VP Level SelectVP 74 Enable Thermal Foldback EnTherm 74 Lock Foldback Adjust LockAdj 74 Foldback Attack Delay AttackDly[1:0] 75 Enable Foldback Floor EnFloor 75 DS726PP2 CS4525 Ramp Speed RmpSpd[1:0] 75 Mixer / Pre-Scale Configuration Address 06h 75 Pre-Scale Attenuation PreScale[2:0] 75 Right Channel Mixer RChMix[1:0] 76 Left Channel Mixer LChMix[1:0] 76 Tone Configuration Address 07h 76 De-Emphasis Control DeEmph 76 Adaptive Loudness Compensation Control Loudness 76 Digital Signal Processing High-Pass Filter EnDigHPF 77 Treble Corner Frequency TrebFc[1:0] 77 Bass Corner Frequency BassFc[1:0] 77 Tone Control Enable EnToneCtrl 77 Tone Control Address 08h 78 Treble Gain Level Treb[3:0] 78 Bass Gain Level Bass[3:0] 78 Bass Manager/Parametric EQ Control Address 09h 78 Freeze Controls Freeze 78 Hi-Z PWM_SIG Outputs HiZPSig 79 Bass Cross-Over Frequency BassMgr[2:0] 79 Enable Channel B Parametric EQ EnChBPEq 79 Enable Channel A Parametric EQ EnChAPEq 79 Volume and 2-Way Cross-Over Configuration Address 55h 80 Soft Ramp and Zero Cross Control SZCMode[1:0] 80 Enable 50% Duty Cycle for Mute Condition Mute50/50 80 Auto-Mute AutoMute 80 Enable 2-Way Crossover En2Way 81 2-Way Cross-Over Frequency 2WayFreq[2:0] 81 Channel A & B 2-Way Sensitivity Control Address 56h 81 Channel A and Channel B Low-Pass Sensitivity Adjust LowPass[3:0] 81 Channel A and Channel B High-Pass Sensitivity Adjust HighPass[3:0] 82 Master Volume Control Address 57h 82 Master Volume Control MVol[7:0] 82 Channel A and B Volume Control Address 58h & 59h 83 Channel X Volume Control ChXVol[7:0] 83 Sub Channel Volume Control Address 5Ah 83 Sub Channel Volume Control SubVol[7:0] 83 Mute/Invert Control Address 5Bh 84 ADC Invert Signal Polarity InvADC 84 Invert Channel PWM Signal Polarity InvChX 84 Invert Sub PWM Signal Polarity InvSub 84 ADC Channel Mute MuteADC 84 Independent Channel A & B Mute MuteChX 84 Sub Channel Mute MuteSub 85 Limiter Configuration 1 Address 5Ch 85 Maximum Threshold Max[2:0] 85 Minimum Threshold Min[2:0] 85 Peak Signal Limit All Channels LimitAll 86 Peak Detect and Limiter Enable EnLimiter 86 Limiter Configuration 2 Address 5Dh 87 Limiter Release Rate RRate[5:0] 87 Limiter Configuration 3 Address 5Eh 87 Enable Thermal Limiter EnThLim 87 Limiter Attack Rate ARate[5:0] 87 Power Control Address 5Fh 88 DS726PP2 CS4525 LIST OF FIGURES Figure 1.Typical Connection Diagram - Software Mode 13 Figure 2.Typical Connection Diagram - Hardware Mode 14 Figure 3.Typical System Configuration 1 15 Figure 4.Typical System Configuration 2 15 Figure 5.Typical System Configuration 3 16 Figure 6.Typical System Configuration 4 17 Figure 7.Serial Audio Input Port Timing 21 Figure 8.AUX Serial Port Interface Master Mode Timing 22 Figure 9.SYS_CLK Timing from Reset 23 Figure 10.PWM_SIGX Timing 23 Figure 11.Control Port Timing - 24 Figure 12.Typical SYS_CLK Input Clocking Configuration 26 Figure 13.Typical Crystal Oscillator Clocking Configuration 27 Figure 14.Digital Signal Flow 29 Figure 15.De-Emphasis Filter 31 Figure 16.Bi-Quad Filter Architecture 33 DS726PP2 CS4525 Figure 17.Peak Signal Detection & Limiting 37 Figure 18.Foldback Process 40 Figure 19.Popguard Connection Diagram 46 Figure 20.2-Channel Full-Bridge PWM Output Delay 50 Figure 21.3-Channel PWM Output Delay 50 Figure 22.Typical SYS_CLK Input Clocking Configuration 54 Figure 23.Hardware Mode PWM Output Delay 55 Figure 24.Hardware Mode Digital Signal Flow 56 Figure 25.Foldback Process 57 Figure 26.Output Filter - Half-Bridge 59 Figure 27.Output Filter - Full-Bridge 60 Figure 28.Recommended Unity Gain Input Filter 61 Figure 29.Recommended 2 VRMS Input Filter 61 Figure Serial Audio Formats 62 Figure 31.Left-Justified Serial Audio Formats 62 Figure 32.Right-Justified Serial Audio Formats 63 Figure 33.Control Port Timing, Write 64 Figure 34.Control Port Timing, Read 64 LIST OF TABLES Table I/O Power Rails 12 Table Bass Shelving Filter Corner Frequencies 31 Table Treble Shelving Filter Corner Frequencies 32 Table Bass Management Cross-Over Frequencies 35 Table 2-Way Cross-Over Frequencies 41 Table Auxiliary Serial Port Data Output 43 Table Nominal Switching Frequencies of the Auxiliary Serial Output 43 Table PWM Power Output Configurations 45 Table Typical Ramp Times for Various VP Voltages 46 Table PWM Logic-Level Output Configurations 49 Table PWM Output Switching Rates and Quantization Levels 51 Table Output of PWM_SIG Outputs 52 Table SYS_CLOCK Frequency Selection 54 Table Input Source Selection 55 Table Serial Audio Interface Format Selection 55 Table Thermal Foldback Enable Selection 57 Table PWM Output Switching Rates and Quantization Levels 58 Table Low-Pass Filter Components - Half-Bridge 59 Table DC-Blocking Capacitors Values - Half-Bridge 59 Table Low-Pass Filter Components - Full-Bridge 60 Table Power Supply Configuration and Settings 63 DS726PP2 PIN DESCRIPTIONS - SOFTWARE MODE CS4525 XTI XTO SYS_CLK AUX_LRCK/AD0 AUX_SCLK AUX_SDOUT DLY_SDIN/EX_TWR DLY_SDOUT PWM_SIG1 PWM_SIG2 PGND 48 47 46 45 44 43 42 41 40 39 38 37 INT 1 SCL 2 SDA 3 LRCK 4 SCLK 5 SDIN 6 HP_DETECT/MUTE 7 RST 8 LVD 9 DGND 10 VD_REG 11 VD 12 Thermal Pad Top-Down Through Package View 48-Pin QFN Package 13 14 15 16 17 18 19 20 21 22 23 24 36 VP 35 OUT1 34 PGND 33 PGND 32 OUT2 31 VP 30 VP 29 OUT3 28 PGND 27 PGND 26 OUT4 25 VP VA_REG AGND FILT+ VQ AFILTL AFILTR AINL AINR OCREF PGND RAMP_CAP Pin Name INT SCL SDA LRCK SCLK SDIN HP_DETECT/ MUTE Pin # Pin Description 1 Interrupt Output - Indicates an interrupt condition has occurred. 2 Serial Control Port Clock Input - Serial clock for the control port. 3 Serial Control Data Input/Output - Bi-directional data I/O for the control port. Left Right Clock Input - Determines which channel, Left or Right, is currently active on the serial audio data line. 5 Serial Clock Input - Serial bit clock for the serial audio interface. 6 Serial Audio Data Input - Input for two’s complement serial audio data. Headphone Detect / Mute Input - Headphone detection or mute input signal as configured via the control port. Reset Input - The device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low. DS726PP2 DGND VD_REG VD VA_REG AGND FILT+ VQ AFILTL AFILTR AINL AINR OCREF PGND RAMP_CAP OUT4 OUT3 OUT2 OUT1 PWM_SIG2 PWM_SIG1 DLY_SDOUT 14.ORDERING INFORMATION Product CS4525 CRD4525-Q1 CRD4525-D1 Description Package Digital Audio Amp with Integrated ADC 48-QFN 4 Layer / 1oz. Copper Reference Design Board 2 Layer / 1oz. Copper Reference Design Board Pb-Free Yes - Grade Commercial Temp Range Container Rail -10° to +70°C Tape and Reel Order# CS4525-CNZ CS4525-CNZR CRD4525-Q1 CRD4525-D1 DS726PP2 15.REVISION HISTORY Release PP1 PP2 Changes The following items were updated “Analog Input Characteristics” on page 19 “PWM Power Output Characteristics” on page 20 “XTI Switching Specifications” on page 23 “SYS_CLK Switching Specifications” on page 23 “Digital Interface Specifications” on page 25 Section “Half-Bridge Output Filter” on page 59 Section “Full-Bridge Output Filter Stereo or Parallel ” on page 60 Table 21, “Power Supply Configuration and Settings,” on page 63 Section “Select VD Level SelectVD ” on page 88 Added Section “Enable Over-Current Protection EnOCProt ” on page 88 CS4525 Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries “Cirrus” believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE “CRITICAL APPLICATIONS” . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. is a registered trademark of Philips Semiconductor. DS726PP2

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CS4525
30 W Digital Audio Amplifier with Integrated ADC

Digital Amplifier Features

Fully Integrated Power MOSFETs No Heatsink Required

Programmable Power Foldback on Thermal Warning

High Efficiency
> 100 dB Dynamic Range < THD+N 1 W Configurable Outputs 10% THD+N
1 x 30 W into 4 Ω, Parallel Full-Bridge 2 x 15 W into 8 Ω, Full-Bridge 2 x 7 W into 4 Ω, Half-Bridge + 1 x 15 W
into 8 Ω, Full-Bridge Built-In Protection with Error Reporting

Overcurrent/Undervoltage/Thermal Overload Shutdown

Thermal Warning Reporting

PWM for Half-Bridge Mode

Click-Free Start-Up

Programmable Channel Delay for System Noise & Radiated Emissions Management

ADC Features

Stereo, 24-bit, 48 kHz Conversion Multi-bit Architecture 95 dB Dynamic Range A-wtd -86 dB THD+N Supports 2 Vrms Input with Passive

Components

System Features

Asynchronous 2-Channel Digital Serial Port 32 kHz to 96 kHz Input Sample Rates Operation with On-Chip Oscillator Driver or

Applied SYS_CLK at or MHz Integrated Sample Rate Converter SRC Eliminates Clock-Jitter Effects Input Sample Rate Independent Operation Simplifies System Integration

Spread Spectrum PWM Modulation Reduces EMI Radiated Energy

Low Quiescent Current

Features continued on page 2

System Clock

Crystal Driver I/O

Stereo Analog In

Serial Audio Clocks & Data

Serial Audio Data I/O

Serial Audio Clocks & Data

HP Detect/Mute

Reset Interrupt or Hardware Configuration

Crystal Oscillator Driver Multi-bit ADC

Serial Audio Input Port Serial Audio

Delay Interface Auxiliary Serial Port

Register /Hardware Configuration

V to 5 V

Audio Processing

Parametric EQ High-Pass Bass/Treble Adaptive Loudness Compensation 2-Ch Mixer Bass Mgr Linkwitz-Riley Crossover De-Emphasis Volume

Multi-bit Modulator
with Integrated Sample Rate Converter

Error Protection
Please refer to “Ordering Information” on page 97 for complete ordering information.

DS726PP2

CS4525

TABLE OF CONTENTS

PIN DESCRIPTIONS - SOFTWARE MODE 8 PIN DESCRIPTIONS - HARDWARE MODE 10

Digital I/O Pin Characteristics 12 TYPICAL CONNECTION DIAGRAMS 13 TYPICAL SYSTEM CONFIGURATION DIAGRAMS 15 CHARACTERISTICS AND SPECIFICATIONS 18 APPLICATIONS 26

Software Mode 26 System Clocking 26 SYS_CLK Input Clock Mode 26 Crystal Oscillator Mode 27 Power-Up and Power-Down 28 Recommended Power-Up Sequence 28 Recommended Power-Down Sequence 28 Input Source Selection 29 Digital Sound Processing 29 Pre-Scaler 30 Digital Signal Processing High-Pass Filter 30 Channel Mixer 30 De-Emphasis 31 Tone Control 31 Parametric EQ 33 Adaptive Loudness Compensation 34 Bass Management 35 Volume and Muting Control 36 Peak Signal Limiter 37 Thermal Limiter 39 Thermal Foldback 40 2-Way Crossover & Sensitivity Control 41 Auxiliary Serial Output 43 Serial Audio Delay & Warning Input Port 44 Serial Audio Delay Interface 44 External Warning Input Port 44 Powered PWM Outputs 45 Output Channel Configurations 45 PWM Popguard Transient Control 45 Logic-Level PWM Outputs 46 Recommended PWM_SIG Power-Up Sequence for an External PWM Amplifier 47 Recommended PWM_SIG Power-Down Sequence for an External PWM Amplifier 47 Recommended PWM_SIG Power-Up Sequence for Headphone & Line-Out 48 Recommended PWM_SIG Power-Down Sequence for Headphone & Line-Out 48 PWM_SIG Logic-Level Output Configurations 49 PWM Modulator Configuration 50 PWM Channel Delay 50 PWM AM Frequency Shift 51 Headphone Detection & Hardware Mute Input 51 Interrupt Reporting 53 Automatic Power Stage Shut-Down 53

Hardware Mode 54 System Clocking 54 Power-Up and Power-Down 54 Recommended Power-Up Sequence 54

DS726PP2

CS4525

Recommended Power-Down Sequence 55 Input Source Selection 55 PWM Channel Delay 55 Digital Signal Flow 56

High-Pass Filter 56 Mute Control 56 Warning and Error Reporting 56 Thermal Foldback 57 Automatic Power Stage Shut-Down 58 PWM Modulators and Sample Rate Converters 58 Output Filters 59 Half-Bridge Output Filter 59 Full-Bridge Output Filter Stereo or Parallel 60 Analog Inputs 61 Serial Audio Interfaces 62 Data Format 62 Left-Justified Data Format 62 Right-Justified Data Format 63 Integrated VD Regulator 63 Control Port Description and Timing 64 PCB LAYOUT CONSIDERATIONS 65 Power Supply, Grounding 65 QFN Thermal Pad 65 REGISTER QUICK REFERENCE 66 REGISTER DESCRIPTIONS 69 Clock Configuration Address 01h 69 SYS_CLK Output Enable EnSysClk 69 SYS_CLK Output Divider DivSysClk 69 Clock Frequency ClkFreq[1:0] 69 HP_Detect/Mute Pin Active Logic Level HP/MutePol 70 HP_Detect/Mute Pin Mode HP/Mute 70 Modulator Phase Shifting PhaseShift 70 AM Frequency Shifting FreqShift 70 Input Configuration Address 02h 71 Input Source Selection ADC/SP 71 ADC High-Pass Filter Enable EnAnHPF 71 Serial Port Sample Rate SPRate[1:0] - Read Only 71 Input Serial Port Digital Interface Format DIF [2:0] 71 AUX Port Configuration Address 03h 72 Enable Aux Serial Port EnAuxPort 72 Delay & Warning Port Configuration DlyPortCfg[1:0] 72 Aux/Delay Serial Port Digital Interface Format 72 Aux Serial Port Right Channel Data Select RChDSel[1:0] 72 Aux Serial Port Left Channel Data Select LChDSel[1:0] 73 Output Configuration Address 04h 73 Output Configuration OutputCfg[1:0] 73 PWM Signals Output Data Select PWMDSel[1:0] 73 Channel Delay Settings OutputDly[3:0] 73 Foldback and Ramp Configuration Address 05h 74 Select VP Level SelectVP 74 Enable Thermal Foldback EnTherm 74 Lock Foldback Adjust LockAdj 74 Foldback Attack Delay AttackDly[1:0] 75 Enable Foldback Floor EnFloor 75

DS726PP2

CS4525

Ramp Speed RmpSpd[1:0] 75 Mixer / Pre-Scale Configuration Address 06h 75

Pre-Scale Attenuation PreScale[2:0] 75 Right Channel Mixer RChMix[1:0] 76 Left Channel Mixer LChMix[1:0] 76 Tone Configuration Address 07h 76 De-Emphasis Control DeEmph 76 Adaptive Loudness Compensation Control Loudness 76 Digital Signal Processing High-Pass Filter EnDigHPF 77 Treble Corner Frequency TrebFc[1:0] 77 Bass Corner Frequency BassFc[1:0] 77 Tone Control Enable EnToneCtrl 77 Tone Control Address 08h 78 Treble Gain Level Treb[3:0] 78 Bass Gain Level Bass[3:0] 78 Bass Manager/Parametric EQ Control Address 09h 78 Freeze Controls Freeze 78 Hi-Z PWM_SIG Outputs HiZPSig 79 Bass Cross-Over Frequency BassMgr[2:0] 79 Enable Channel B Parametric EQ EnChBPEq 79 Enable Channel A Parametric EQ EnChAPEq 79 Volume and 2-Way Cross-Over Configuration Address 55h 80 Soft Ramp and Zero Cross Control SZCMode[1:0] 80 Enable 50% Duty Cycle for Mute Condition Mute50/50 80 Auto-Mute AutoMute 80 Enable 2-Way Crossover En2Way 81 2-Way Cross-Over Frequency 2WayFreq[2:0] 81 Channel A & B 2-Way Sensitivity Control Address 56h 81 Channel A and Channel B Low-Pass Sensitivity Adjust LowPass[3:0] 81 Channel A and Channel B High-Pass Sensitivity Adjust HighPass[3:0] 82 Master Volume Control Address 57h 82 Master Volume Control MVol[7:0] 82 Channel A and B Volume Control Address 58h & 59h 83 Channel X Volume Control ChXVol[7:0] 83 Sub Channel Volume Control Address 5Ah 83 Sub Channel Volume Control SubVol[7:0] 83 Mute/Invert Control Address 5Bh 84 ADC Invert Signal Polarity InvADC 84 Invert Channel PWM Signal Polarity InvChX 84 Invert Sub PWM Signal Polarity InvSub 84 ADC Channel Mute MuteADC 84 Independent Channel A & B Mute MuteChX 84 Sub Channel Mute MuteSub 85 Limiter Configuration 1 Address 5Ch 85 Maximum Threshold Max[2:0] 85 Minimum Threshold Min[2:0] 85 Peak Signal Limit All Channels LimitAll 86 Peak Detect and Limiter Enable EnLimiter 86 Limiter Configuration 2 Address 5Dh 87 Limiter Release Rate RRate[5:0] 87 Limiter Configuration 3 Address 5Eh 87 Enable Thermal Limiter EnThLim 87 Limiter Attack Rate ARate[5:0] 87 Power Control Address 5Fh 88

DS726PP2

CS4525
LIST OF FIGURES

Figure 1.Typical Connection Diagram - Software Mode 13 Figure 2.Typical Connection Diagram - Hardware Mode 14 Figure 3.Typical System Configuration 1 15 Figure 4.Typical System Configuration 2 15 Figure 5.Typical System Configuration 3 16 Figure 6.Typical System Configuration 4 17 Figure 7.Serial Audio Input Port Timing 21 Figure 8.AUX Serial Port Interface Master Mode Timing 22 Figure 9.SYS_CLK Timing from Reset 23 Figure 10.PWM_SIGX Timing 23 Figure 11.Control Port Timing - 24 Figure 12.Typical SYS_CLK Input Clocking Configuration 26 Figure 13.Typical Crystal Oscillator Clocking Configuration 27 Figure 14.Digital Signal Flow 29 Figure 15.De-Emphasis Filter 31 Figure 16.Bi-Quad Filter Architecture 33

DS726PP2

CS4525

Figure 17.Peak Signal Detection & Limiting 37 Figure 18.Foldback Process 40 Figure 19.Popguard Connection Diagram 46 Figure 20.2-Channel Full-Bridge PWM Output Delay 50 Figure 21.3-Channel PWM Output Delay 50 Figure 22.Typical SYS_CLK Input Clocking Configuration 54 Figure 23.Hardware Mode PWM Output Delay 55 Figure 24.Hardware Mode Digital Signal Flow 56 Figure 25.Foldback Process 57 Figure 26.Output Filter - Half-Bridge 59 Figure 27.Output Filter - Full-Bridge 60 Figure 28.Recommended Unity Gain Input Filter 61 Figure 29.Recommended 2 VRMS Input Filter 61 Figure Serial Audio Formats 62 Figure 31.Left-Justified Serial Audio Formats 62 Figure 32.Right-Justified Serial Audio Formats 63 Figure 33.Control Port Timing, Write 64 Figure 34.Control Port Timing, Read 64

LIST OF TABLES

Table I/O Power Rails 12 Table Bass Shelving Filter Corner Frequencies 31 Table Treble Shelving Filter Corner Frequencies 32 Table Bass Management Cross-Over Frequencies 35 Table 2-Way Cross-Over Frequencies 41 Table Auxiliary Serial Port Data Output 43 Table Nominal Switching Frequencies of the Auxiliary Serial Output 43 Table PWM Power Output Configurations 45 Table Typical Ramp Times for Various VP Voltages 46 Table PWM Logic-Level Output Configurations 49 Table PWM Output Switching Rates and Quantization Levels 51 Table Output of PWM_SIG Outputs 52 Table SYS_CLOCK Frequency Selection 54 Table Input Source Selection 55 Table Serial Audio Interface Format Selection 55 Table Thermal Foldback Enable Selection 57 Table PWM Output Switching Rates and Quantization Levels 58 Table Low-Pass Filter Components - Half-Bridge 59 Table DC-Blocking Capacitors Values - Half-Bridge 59 Table Low-Pass Filter Components - Full-Bridge 60 Table Power Supply Configuration and Settings 63

DS726PP2

PIN DESCRIPTIONS - SOFTWARE MODE

CS4525

XTI XTO SYS_CLK AUX_LRCK/AD0 AUX_SCLK AUX_SDOUT DLY_SDIN/EX_TWR DLY_SDOUT PWM_SIG1 PWM_SIG2 PGND
48 47 46 45 44 43 42 41 40 39 38 37

INT 1 SCL 2 SDA 3 LRCK 4 SCLK 5 SDIN 6 HP_DETECT/MUTE 7 RST 8 LVD 9 DGND 10 VD_REG 11

VD 12

Thermal Pad

Top-Down Through Package View 48-Pin QFN Package
13 14 15 16 17 18 19 20 21 22 23 24
36 VP 35 OUT1 34 PGND 33 PGND 32 OUT2 31 VP 30 VP 29 OUT3 28 PGND 27 PGND 26 OUT4 25 VP

VA_REG AGND FILT+ VQ AFILTL AFILTR AINL AINR

OCREF PGND

RAMP_CAP

Pin Name INT SCL SDA

LRCK

SCLK SDIN HP_DETECT/ MUTE

Pin #

Pin Description
1 Interrupt Output - Indicates an interrupt condition has occurred.
2 Serial Control Port Clock Input - Serial clock for the control port.
3 Serial Control Data Input/Output - Bi-directional data I/O for the control port.

Left Right Clock Input - Determines which channel, Left or Right, is currently active on the serial audio data line.
5 Serial Clock Input - Serial bit clock for the serial audio interface.
6 Serial Audio Data Input - Input for two’s complement serial audio data.

Headphone Detect / Mute Input - Headphone detection or mute input signal as configured via the control port.

Reset Input - The device enters a low power mode and all internal registers are reset to their default settings when this pin is driven low.

DS726PP2

DGND VD_REG VD VA_REG AGND

FILT+

VQ AFILTL AFILTR AINL AINR OCREF

PGND

RAMP_CAP

OUT4 OUT3 OUT2 OUT1 PWM_SIG2 PWM_SIG1 DLY_SDOUT
14.ORDERING INFORMATION

Product CS4525 CRD4525-Q1 CRD4525-D1

Description Package

Digital Audio Amp with Integrated ADC
48-QFN
4 Layer / 1oz. Copper

Reference Design

Board
2 Layer / 1oz. Copper

Reference Design

Board

Pb-Free Yes -

Grade Commercial

Temp Range Container

Rail -10° to +70°C Tape and

Reel

Order# CS4525-CNZ CS4525-CNZR

CRD4525-Q1

CRD4525-D1

DS726PP2
15.REVISION HISTORY

Release PP1 PP2

Changes

The following items were updated “Analog Input Characteristics” on page 19 “PWM Power Output Characteristics” on page 20 “XTI Switching Specifications” on page 23 “SYS_CLK Switching Specifications” on page 23 “Digital Interface Specifications” on page 25 Section “Half-Bridge Output Filter” on page 59 Section “Full-Bridge Output Filter Stereo or Parallel ” on page 60 Table 21, “Power Supply Configuration and Settings,” on page 63 Section “Select VD Level SelectVD ” on page 88

Added Section “Enable Over-Current Protection EnOCProt ” on page 88

CS4525

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to

IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries “Cirrus” believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

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DS726PP2

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Datasheet ID: CS4525-CNZR 523189