74F322PC

74F322PC Datasheet

74F322 Octal Serial/Parallel Register with Sign Extend

Part	Datasheet
74F322PC	74F322PC (pdf)

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74F322 Octal Serial/Parallel Register with Sign Extend 74F322 Octal Serial/Parallel Register with Sign Extend The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-STATE parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible hold store , shift right with serial entry, shift right with sign extend and parallel load. An asynchronous Master Reset MR input overrides clocked operation and clears the register. s Multiplexed parallel I/O ports s Separate serial input and output s Sign extend function s 3-STATE outputs for bus applications Ordering Code: Order Number Package Number Package Description 74F322PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 1999 Fairchild Semiconductor Corporation DS009516.prf 74F322 Unit Loading/Fan Out Pin Names RE S/P SE S D0, D1 CP MR OE Q0 Register Enable Input Active LOW Serial HIGH or Parallel LOW Mode Control Input Sign Extend Input Active LOW Serial Data Select Input Serial Data Inputs Clock Pulse Input Active Rising Edge Asynchronous Master Reset Input Active LOW 3-STATE Output Enable Input Active LOW Bi-State Serial Output Multiplexed Parallel Data Inputs or 3-STATE Parallel Data Outputs U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.8 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/−20 mA 70 µA/−0.65 mA −3 mA/24 mA 20 mA Functional Description The 74F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on RE enables shifting or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S/P enables shift right, while a LOW signal disables the 3-STATE output buffers and enables parallel loading. In the shift right mode a HIGH sig- nal on SE enables serial entry from either D0 or D1, as determined by the S input. A LOW signal on SE enables shift right but Q7 reloads its contents, thus performing the sign extend function required for the 74F384 Twos Complement Multiplier. A HIGH signal on OE disables the 3STATE output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed. Mode Select Table Mode Inputs MR RE S/P SE S Outputs CP I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Q0 Note 1 Clear LXXXX LXXXX Parallel H L X Load Shift Right Sign H L HH L H L HHH HLHLX D0 D1 O7 Extend Hold H = HIGH Voltage Level L = LOW Voltage Level = High Impedance Output State = LOW-to-HIGH Transition NC = No Change Note = The level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs except Q0 are isolated from the I/O terminal. Note D0, D1 = The level of the steady-state inputs to the serial multiplexer input. Note = The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition. Note 1 When the OE input is HIGH all I/On terminals are at the high impedance state sequential operation or clearing of the register is not affected. 74F322 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F322 Absolute Maximum Ratings Note 2 Storage Temperature −65°C to +150°C Ambient Temperature under Bias

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74F322 Octal Serial/Parallel Register with Sign Extend
74F322 Octal Serial/Parallel Register with Sign Extend

The 74F322 is an 8-bit shift register with provision for either serial or parallel loading and with 3-STATE parallel outputs plus a bi-state serial output. Parallel data inputs and parallel outputs are multiplexed to minimize pin count. State changes are initiated by the rising edge of the clock. Four synchronous modes of operation are possible hold store , shift right with serial entry, shift right with sign extend and
parallel load. An asynchronous Master Reset MR input overrides clocked operation and clears the register.
s Multiplexed parallel I/O ports s Separate serial input and output s Sign extend function s 3-STATE outputs for bus applications
Ordering Code:

Order Number Package Number

Package Description
74F322PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
1999 Fairchild Semiconductor Corporation DS009516.prf
74F322

Unit Loading/Fan Out

Pin Names

RE S/P SE S D0, D1 CP MR OE Q0

Register Enable Input Active LOW Serial HIGH or Parallel LOW Mode Control Input Sign Extend Input Active LOW Serial Data Select Input Serial Data Inputs Clock Pulse Input Active Rising Edge Asynchronous Master Reset Input Active LOW 3-STATE Output Enable Input Active LOW Bi-State Serial Output Multiplexed Parallel Data Inputs or 3-STATE Parallel Data Outputs

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.8 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/−20 mA 70 µA/−0.65 mA −3 mA/24 mA 20 mA

Functional Description

The 74F322 contains eight D-type edge triggered flip-flops and the interstage gating required to perform right shift and the intrastage gating necessary for hold and synchronous parallel load operations. A LOW signal on RE enables shifting or parallel loading, while a HIGH signal enables the hold mode. A HIGH signal on S/P enables shift right, while a LOW signal disables the 3-STATE output buffers and enables parallel loading. In the shift right mode a HIGH sig-
nal on SE enables serial entry from either D0 or D1, as determined by the S input. A LOW signal on SE enables shift right but Q7 reloads its contents, thus performing the sign extend function required for the 74F384 Twos Complement Multiplier. A HIGH signal on OE disables the 3STATE output buffers, regardless of the other control inputs. In this condition the shifting and loading operations can still be performed.

Mode Select Table

Mode

Inputs MR RE S/P SE S

Outputs

CP I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Q0

Note 1

Clear

LXXXX

LXXXX Parallel H L X

Load Shift Right Sign

H L HH L H L HHH HLHLX

D0 D1 O7

Extend

Hold

H = HIGH Voltage Level L = LOW Voltage Level
= High Impedance Output State = LOW-to-HIGH Transition NC = No Change Note = The level of the steady-state input at the respective I/O terminal is loaded into the flip-flop while the flip-flop outputs except Q0 are isolated from the I/O terminal. Note D0, D1 = The level of the steady-state inputs to the serial multiplexer input. Note = The level of the respective Qn flip-flop prior to the last Clock LOW-to-HIGH transition.

Note 1 When the OE input is HIGH all I/On terminals are at the high impedance state sequential operation or clearing of the register is not affected.
74F322

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F322

Absolute Maximum Ratings Note 2

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias

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Datasheet ID: 74F322PC 513316