74F273PC

74F273PC Datasheet

74F273 Octal D-Type Flip-Flop

Part	Datasheet
74F273PC	74F273PC (pdf)

Related Parts	Information
74F273SJ	74F273SJ
74F273SJX	74F273SJX
74F273SC	74F273SC
74F273SCX	74F273SCX

PDF Datasheet Preview
74F273 Octal D-Type Flip-Flop 74F273 Octal D-Type Flip-Flop The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset MR inputs load and reset clear all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. s Ideal buffer for MOS microprocessor or memory s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous Master Reset s See 74F377 for clock enable version s See 74F373 for transparent latch version s See 74F374 for 3-STATE version Ordering Code: Order Number Package Number Package Description 74F273SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F273SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F273PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009511 74F273 Unit Loading/Fan Out Pin Names MR CP Data Inputs Master Reset Active LOW Clock Pulse Input Active Rising Edge Data Outputs Mode Select-Function Table U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Operating Mode Inputs Output Reset Clear Load “1” Load “0” H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition = Immaterial = LOW-to-HIGH clock transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F273 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA ESD Last Passing Voltage min 4000V

PDF Datasheet Preview

74F273 Octal D-Type Flip-Flop
74F273 Octal D-Type Flip-Flop

The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset MR inputs load and reset clear all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.

All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
s Ideal buffer for MOS microprocessor or memory s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous Master Reset s See 74F377 for clock enable version s See 74F373 for transparent latch version s See 74F374 for 3-STATE version
Ordering Code:

Order Number Package Number

Package Description
74F273SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F273SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F273PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009511
74F273

Unit Loading/Fan Out

Pin Names

MR CP

Data Inputs Master Reset Active LOW Clock Pulse Input Active Rising Edge Data Outputs

Mode Select-Function Table

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA

Operating Mode

Inputs

Output

Reset Clear Load “1” Load “0”

H = HIGH Voltage Level steady state h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition L = LOW Voltage Level steady state I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition
= Immaterial = LOW-to-HIGH clock transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F273

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

ESD Last Passing Voltage min
4000V

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Datasheet ID: 74F273PC 513310