74F257ASJ

74F257ASJ Datasheet

74F257A Quad 2-Input Multiplexer with 3-STATE Outputs

Part	Datasheet
74F257ASJ	74F257ASJ (pdf)

Related Parts	Information
74F257APC	74F257APC
74F257ASC	74F257ASC
74F257ASCX	74F257ASCX
74F257ASJX	74F257ASJX

PDF Datasheet Preview
74F257A Quad 2-Input Multiplexer with 3-STATE Outputs 74F257A Quad 2-Input Multiplexer with 3-STATE Outputs The 74F257A is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true non-inverted form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable OE input, allowing the outputs to interface directly with bus-oriented systems. s Multiplexer expansion by tying outputs together s Non-inverting 3-STATE outputs s Input clamp diodes limit high-speed termination effects Ordering Code: Order Number Package Number Package Description 74F257ASC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F257ASJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F257APC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009507 74F257A Unit Loading/Fan Out Pin Names Common Data Select Input 3-STATE Output Enable Input Active LOW Data Inputs from Source 0 Data Inputs from Source 1 3-STATE Multiplexer Outputs U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA Truth Table Output Enable Select Input H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Data Inputs Output Z L H L H Functional Description The 74F257A is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a Common Data Select input. When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in true noninverted form. The device is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equation for the outputs is shown below: Zn = OE • In• S + Ion • S When the Output Enable input OE is HIGH, the outputs are forced to a high impedance OFF state. If the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure the Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F257A Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output

PDF Datasheet Preview

74F257A Quad 2-Input Multiplexer with 3-STATE Outputs
74F257A Quad 2-Input Multiplexer with 3-STATE Outputs

The 74F257A is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a Common Data Select input. The four outputs present the selected data in true non-inverted form. The outputs may be switched to a high impedance state with a HIGH on the common Output Enable OE input, allowing the outputs to interface directly with bus-oriented systems.
s Multiplexer expansion by tying outputs together s Non-inverting 3-STATE outputs s Input clamp diodes limit high-speed termination effects
Ordering Code:

Order Number Package Number

Package Description
74F257ASC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F257ASJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F257APC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009507
74F257A

Unit Loading/Fan Out

Pin Names

Common Data Select Input 3-STATE Output Enable Input Active LOW Data Inputs from Source 0 Data Inputs from Source 1 3-STATE Multiplexer Outputs

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA

Truth Table

Output Enable

Select Input

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Data Inputs

Output

Z L H L H

Functional Description

The 74F257A is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a Common Data Select input. When the Select input is LOW, the I0x inputs are selected and when Select is HIGH, the I1x inputs are selected. The data on the selected inputs appears at the outputs in true noninverted form. The device is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equation for the outputs is shown below:

Zn = OE
• In• S + Ion
• S

When the Output Enable input OE is HIGH, the outputs are forced to a high impedance OFF state. If the outputs are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings. Designers should ensure the Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F257A

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74F257ASJ Datasheet file may be downloaded here without warranties.

Datasheet ID: 74F257ASJ 513307