74F251APC

74F251APC Datasheet

74F251A 8-Input Multiplexer with 3-STATE Outputs

Part	Datasheet
74F251APC	74F251APC (pdf)

Related Parts	Information
74F251ASC	74F251ASC
74F251ASCX	74F251ASCX
74F251ASJ	74F251ASJ
74F251ASJX	74F251ASJX

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74F251A 8-Input Multiplexer with 3-STATE Outputs 74F251A 8-Input Multiplexer with 3-STATE Outputs The 74F251A is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided. s Multifunctional capability s On-chip select logic decoding s Inverting and non-inverting 3-STATE outputs Ordering Code: Order Number Package Number Package Description 74F251ASC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F251ASJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F251APC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009504 74F251A Unit Loading/Fan Out Pin Names Select Inputs 3-STATE Output Enable Input Active LOW Multiplexer Inputs 3-STATE Multiplexer Output Complementary 3-STATE Multiplexer Output U.L. HIGH/LOW 150/40 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA −3 mA/24 mA 20 mA Functional Description Truth Table This device is a logical implementation of a single-pole, 8position switch with the switch position controlled by the Inputs Outputs state of three Select inputs, S0, S1, S2. Both assertion and negation outputs are provided. The Output Enable input OE is active LOW. When it is activated, the logic function provided at the output is: Z = OE • I0•S0•S1 •S2 + I1•S0•S 1•S2 + I2•S0•S1•S2 + I3•S0•S1•S2 + I4•S0•S1•S2 + I5•S0•S1•S2 + I6•S0•S1•S2 + I7•S0•S1•S2 When the Output Enable is HIGH, both outputs are in the high impedance High Z state. This feature allows multi- plexer expansion by tying the outputs of up to 128 devices together. When the outputs of the 3-STATE devices are tied together, all but one device must be in the high imped- H = HIGH Voltage Level ance state to avoid high currents that would exceed the L = LOW Voltage Level maximum ratings. The Output Enable signals should be X = Immaterial designed to ensure there is no overlap in the active LOW Z = High Impedance portion of the enable voltages. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F251A Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2

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74F251A 8-Input Multiplexer with 3-STATE Outputs
74F251A 8-Input Multiplexer with 3-STATE Outputs

The 74F251A is a high-speed 8-input digital multiplexer. It provides, in one package, the ability to select one bit of data from up to eight sources. It can be used as a universal function generator to generate any logic function of four variables. Both assertion and negation outputs are provided.
s Multifunctional capability s On-chip select logic decoding s Inverting and non-inverting 3-STATE outputs
Ordering Code:

Order Number Package Number

Package Description
74F251ASC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F251ASJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F251APC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009504
74F251A

Unit Loading/Fan Out

Pin Names

Select Inputs 3-STATE Output Enable Input Active LOW Multiplexer Inputs 3-STATE Multiplexer Output Complementary 3-STATE Multiplexer Output

U.L. HIGH/LOW
150/40 150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA −3 mA/24 mA 20 mA

Functional Description

Truth Table

This device is a logical implementation of a single-pole, 8position switch with the switch position controlled by the

Inputs

Outputs
state of three Select inputs, S0, S1, S2. Both assertion and
negation outputs are provided. The Output Enable input OE is active LOW. When it is activated, the logic function provided at the output is:

Z = OE
• I0•S0•S1
•S2 + I1•S0•S 1•S2 + I2•S0•S1•S2 + I3•S0•S1•S2 +

I4•S0•S1•S2 + I5•S0•S1•S2 + I6•S0•S1•S2 + I7•S0•S1•S2 When the Output Enable is HIGH, both outputs are in the high impedance High Z state. This feature allows multi-
plexer expansion by tying the outputs of up to 128 devices
together. When the outputs of the 3-STATE devices are
tied together, all but one device must be in the high imped- H = HIGH Voltage Level
ance state to avoid high currents that would exceed the L = LOW Voltage Level
maximum ratings. The Output Enable signals should be X = Immaterial
designed to ensure there is no overlap in the active LOW Z = High Impedance
portion of the enable voltages.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F251A

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2

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Datasheet ID: 74F251APC 513304