74F194PC

74F194PC Datasheet

74F194 4-Bit Bidirectional Universal Shift Register

Part	Datasheet
74F194PC	74F194PC (pdf)

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74F194 4-Bit Bidirectional Universal Shift Register 74F194 4-Bit Bidirectional Universal Shift Register The 74F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed, multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers. s Typical shift frequency of 150 MHz s Asynchronous master reset s Hold do nothing mode s Fully synchronous serial or parallel data transfers Ordering Code: Order Number Package Number Package Description 74F194SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F194PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2004 Fairchild Semiconductor Corporation DS009498 74F194 Unit Loading/Fan Out Pin Names S0, S1 DSR DSL CP Mode Control Inputs Parallel Data Inputs Serial Data Input Shift Right Serial Data Input Shift Left Clock Pulse Input Active Rising Edge Asynchronous Master Reset Input Active LOW Parallel Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Functional Description The 74F194 contains four edge-triggered D-type flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select S0, S1 inputs determine the type of operation, as shown in the Mode Select Table. Signals on the Select, Parallel data and Serial data DSR, DSL inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset MR overrides all other inputs and forces the outputs LOW. Mode Select Table Operating Inputs Outputs Mode MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 Reset L XX X XLLLL Hold H l X q0 q1 q2 q3 Shift Left H l X l X q1 q2 q3 L H l X h X q1 q2 q3 H Shift Right H l h l X L q0 q1 q2 H l h X H q0 q1 q2 Parallel Load H X pn p0 p1 p2 p3 H = HIGH Voltage Level L = LOW Voltage Level pn qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F194 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C

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74F194 4-Bit Bidirectional Universal Shift Register
74F194 4-Bit Bidirectional Universal Shift Register

The 74F194 is a high-speed 4-bit bidirectional universal shift register. As a high-speed, multifunctional, sequential building block, it is useful in a wide variety of applications. It may be used in serial-serial, shift left, shift right, serial-parallel, parallel-serial, and parallel-parallel data register transfers.
s Typical shift frequency of 150 MHz s Asynchronous master reset s Hold do nothing mode s Fully synchronous serial or parallel data transfers
Ordering Code:

Order Number Package Number

Package Description
74F194SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F194PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2004 Fairchild Semiconductor Corporation DS009498
74F194

Unit Loading/Fan Out

Pin Names

S0, S1 DSR DSL CP

Mode Control Inputs Parallel Data Inputs Serial Data Input Shift Right Serial Data Input Shift Left Clock Pulse Input Active Rising Edge Asynchronous Master Reset Input Active LOW Parallel Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA

Functional Description

The 74F194 contains four edge-triggered D-type flip-flops and the necessary interstage logic to synchronously perform shift right, shift left, parallel load and hold operations. Signals applied to the Select S0, S1 inputs determine the type of operation, as shown in the Mode Select Table. Signals on the Select, Parallel data and Serial data DSR, DSL inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset MR overrides all other inputs and forces the outputs LOW.

Mode Select Table

Operating

Inputs

Outputs

Mode

MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3

Reset

L XX X XLLLL

Hold

H l X q0 q1 q2 q3

Shift Left

H l X l X q1 q2 q3 L

H l X h X q1 q2 q3 H

Shift Right H l h l X L q0 q1 q2

H l h X H q0 q1 q2

Parallel Load H X pn p0 p1 p2 p3

H = HIGH Voltage Level L = LOW Voltage Level pn qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. X = Immaterial

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F194

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

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Datasheet ID: 74F194PC 513298