74F181SPC

74F181SPC Datasheet

74F181 4-Bit Arithmetic Logic Unit

Part	Datasheet
74F181SPC	74F181SPC (pdf)

Related Parts	Information
74F181PC	74F181PC

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74F181 4-Bit Arithmetic Logic Unit 74F181 4-Bit Arithmetic Logic Unit The 74F181 is a 4-bit Arithmetic logic Unit ALU which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations. It is 40% faster than the Schottky ALU and only consumes 30% as much power. s Full lookahead for high-speed arithmetic operation on long words Ordering Code: Order Number 74F181PC 74F181SPC Package Number Package Description N24A 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-011, Wide N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Logic Symbols Connection Diagram Active-HIGH Operands Active-LOW Operands IEEE/IEC 2004 Fairchild Semiconductor Corporation DS009491 74F181 Unit Loading/Fan Out Pin Names M Cn A=B G P Cn + 4 Note 1 OC-Open Collector A Operand Inputs Active LOW B Operand Inputs Active LOW Function Select Inputs Mode Control Input Carry Input Function Outputs Active LOW Comparator Output Carry Generate Output Active LOW Carry Propagate Output Active LOW Carry Output U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−1.8 mA 20 µA/−1.8 mA 20 µA/−2.4 mA 20 µA/−0.6 mA 20 µA/−3.0 mA −1 mA/20 mA OC Note 1 /20 mA −1 mA/20 mA −1 mA/20 mA −1 mA/20 mA Functional Description The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit ALU . Controlled by the four Function Select inputs and the Mode Control input M , it can perform all the 16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active LOW operands. The Function Table lists these operations. When the Mode Control input M is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn + 4 output, or for carry lookahead between packages using the signals P Carry Propagate and G Carry Generate . In the Add mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the Subtract mode P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed requirements are not stringent, the 74F181 can be used in a simple Ripple Carry mode by connecting the Carry output Cn+4 signal to the Carry input Cn of the next unit. For high speed operation the device is used in conjunction with a carry lookahead circuit. One carry lookahead package is required for each group of four 74F181 devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths. The A = B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode. The A = B output is open collector and can be wired AND with other A = B outputs to give a comparison for more than four bits. The A = B signal can also be used with the Cn+4 signal to indicate A > B and A < B. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 2s complement notation without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition 1s complement , a carry out means borrow thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol. 74F181 Operation Table a. All Input Data Inverted b. All Input Data True Logic Arithmetic S0 S1 S2 S3 M=H M=L, C0=Inactive Arithmetic M=L, C0=Active LLLL A minus 1 H L A•B

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74F181 4-Bit Arithmetic Logic Unit
74F181 4-Bit Arithmetic Logic Unit

The 74F181 is a 4-bit Arithmetic logic Unit ALU which can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations. It is 40% faster than the Schottky ALU and only consumes 30% as much power.
s Full lookahead for high-speed arithmetic operation on long words
Ordering Code:

Order Number 74F181PC 74F181SPC

Package Number

Package Description

N24A
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-011, Wide

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide

Logic Symbols

Connection Diagram

Active-HIGH Operands

Active-LOW Operands

IEEE/IEC
2004 Fairchild Semiconductor Corporation DS009491
74F181

Unit Loading/Fan Out

Pin Names

M Cn A=B G P Cn + 4

Note 1 OC-Open Collector

A Operand Inputs Active LOW B Operand Inputs Active LOW Function Select Inputs Mode Control Input Carry Input Function Outputs Active LOW Comparator Output Carry Generate Output Active LOW Carry Propagate Output Active LOW Carry Output

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL
20 µA/−1.8 mA 20 µA/−1.8 mA 20 µA/−2.4 mA 20 µA/−0.6 mA 20 µA/−3.0 mA −1 mA/20 mA

OC Note 1 /20 mA
−1 mA/20 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit ALU . Controlled by the four Function Select inputs and the Mode Control input M , it can perform all the 16 possible logic operations or 16 different arithmetic operations on Active HIGH or Active LOW operands. The Function Table lists these operations.

When the Mode Control input M is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn + 4 output, or for carry lookahead between packages using the signals P Carry Propagate and G Carry Generate . In the Add mode, P indicates that F is 15 or more, while G indicates that F is 16 or more. In the Subtract mode P indicates that F is zero or less, while G indicates that F is less than zero. P and G are not affected by carry in. When speed requirements are not stringent, the 74F181 can be used in a simple Ripple Carry mode by connecting the Carry output Cn+4 signal to the Carry input Cn of the next unit. For high speed operation the device is used in conjunction with a carry lookahead circuit. One carry lookahead package is required for each group of four 74F181
devices. Carry lookahead can be provided at various levels and offers high speed capability over extremely long word lengths.

The A = B output from the device goes HIGH when all four F outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the Subtract mode. The A = B output is open collector and can be wired AND with other A = B outputs to give a comparison for more than four bits. The A = B signal can also be used with the Cn+4 signal to indicate A > B and A < B.

The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 2s complement notation without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition 1s complement , a carry out means borrow thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated, this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol.
74F181

Operation Table
a. All Input Data Inverted b. All Input Data True

Logic

Arithmetic

S0 S1 S2 S3 M=H M=L, C0=Inactive

Arithmetic M=L, C0=Active

LLLL

A minus 1

H L A•B

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Datasheet ID: 74F181SPC 513290