74F175SC

74F175SC Datasheet

74F175 Quad D-Type Flip-Flop

Part	Datasheet
74F175SC	74F175SC (pdf)

Related Parts	Information
74F175SJ	74F175SJ
74F175SCX	74F175SCX
74F175SJX	74F175SJX
74F175PC	74F175PC

PDF Datasheet Preview
74F175 Quad D-Type Flip-Flop 74F175 Quad D-Type Flip-Flop The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, LOW. s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s Asynchronous common reset s True and complement output Ordering Code: Order Number Package Number Package Description 74F175SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F175SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F175PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009490 74F175 Unit Loading/Fan Out Pin Names CP MR Data Inputs Clock Pulse Input Active Rising Edge Master Reset Input Active LOW True Outputs Complement Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA Functional Description The 74F175 consists of four edge-triggered D-type flipflops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock CP transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset MR will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The 74F175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Truth Table Inputs H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Clock Transition Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F175 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage

PDF Datasheet Preview

74F175 Quad D-Type Flip-Flop
74F175 Quad D-Type Flip-Flop

The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, LOW.
s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s Asynchronous common reset s True and complement output
Ordering Code:

Order Number Package Number

Package Description
74F175SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F175SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F175PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009490
74F175

Unit Loading/Fan Out

Pin Names

CP MR

Data Inputs Clock Pulse Input Active Rising Edge Master Reset Input Active LOW True Outputs Complement Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

The 74F175 consists of four edge-triggered D-type flipflops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW-to-HIGH clock CP transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset MR will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The 74F175 is useful for general logic applications where a common Master Reset and Clock are acceptable.

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Clock Transition

Outputs

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F175

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

Recommended Operating Conditions

Free Air Ambient Temperature Supply Voltage

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Datasheet ID: 74F175SC 513289