AT91SAM9G45-EKES

AT91SAM9G45-EKES Datasheet

AT91 ARM Thumb-based Microcontrollers

Part	Datasheet
AT91SAM9G45-EKES	AT91SAM9G45-EKES (pdf)

Related Parts	Information
AT91SAM9G45-CU	AT91SAM9G45-CU
AT91SAM9G45-CU-999	AT91SAM9G45-CU-999

PDF Datasheet Preview
• 400 MHz ARM926EJ-S Processor 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC One 64-KByte internal SRAM, single-cycle access at system speed or processor speed through TCM interface One 64-KByte internal ROM, embedding bootstrap routine • Peripherals LCD Controller supporting STN and TFT displays up to 1280*860 ITU-R BT. 601/656 Image Sensor Interface USB Device High Speed, USB Host High Speed and USB Host Full Speed with OnChip Transceiver 10/100 Mbps Ethernet MAC Controller Two High Speed Memory Card Hosts SDIO, SDCard, MMC AC'97 controller Two Master/Slave Serial Peripheral Interfaces Two Three-channel 16-bit Timer/Counters Two Synchronous Serial Controllers I2S mode Four-channel 16-bit PWM Controller Two-wire Interfaces Four USARTs with ISO7816, IrDA, Manchester and SPI modes 8-channel 10-bit ADC with 4-wire Touch Screen support • System 133 MHz twelve 32-bit layer AHB Bus Matrix 37 DMA Channels Boot from NAND Flash, SDCard, or serial DataFlash Reset Controller with on-chip Power-on Reset Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators Internal Low-power 32 kHz RC Oscillator One PLL for the system and one 480 MHz PLL optimized for USB High Speed Two Programmable External Clock Signals Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock • I/O Five 32-bit Parallel Input/Output Controllers 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input • Package 324-ball TFBGA, pitch mm AT91 ARM Thumb-based Microcontrollers AT91SAM9G45 The ARM926EJ-S based AT91SAM9G45 features the frequently demanded combination of user interface functionality and high data rate connectivity, including LCD Controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400MHz and multiple 100+ Mbps data rate peripherals, the AT91SAM9G45 has the performance and bandwidth to the network or local storage media to provide an adequate user experience. The AT91SAM9G45 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and distributed memory including a 64KByte SRAM which can be configured as a tightly coupled memory TCM sustains the high bandwidth required by the processor and the high speed peripherals. The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports ball pitch package for low cost PCB manufacturing. The AT91SAM9G45 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes. 2 AT91SAM9G45 NTRST TTTTCDDMIKSO RTCK JTAGSEL BMS VHHFBHSGSDDPPAA,,HHFHSSDDMMAA Block Diagram Figure AT91SAM9G45 Block Diagram TST PCK0-PCK1 FIQ IRQ DRXD DTXD XIN XOUT XIN32 XOUT32 SHDN WKUP VDDBU NRST VDDCORE System Controller JTAG / Boundary Scan HS Transceiver HS Transceiver DBGU PLLA PLLUTMI OSC12M RC OSC 32K SHDC 4 GPBR RTT RSTC PIOA PIOB PIOC PIOD PIOE In-Circuit Emulator ARM926EJ-S ICache DCache 32 Kbytes MMU 32 Kbytes ITCM DTCM Bus Interface PA PB HS EHCI USB HOST SRAM 64KB Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. Table Mode Default Mode1 Mode2 Mode3 Data Ordering in YCbCr Mode Byte 0 Byte 1 Byte 2 Cr i Cb i Y i+1 Y i+1 Byte 3 Y i+1 Y i+1 Cr i Cb i Table Mode RGB 8:8:8 RGB Format in Default Mode, RGB_CFG = 00, No Swap Byte Byte 0 Byte 1 Byte 2 Byte 3 R7 i+1 R6 i+1 R5 i+1 R4 i+1 D3 R3 i G3 i B3 i R3 i+1 D2 R2 i G2 i B2 i R2 i+1 D1 R1 i G1 i B1 i R1 i+1 D0 R0 i G0 i B0 i R0 i+1 AT91SAM9G45 Table RGB 5:6:5 RGB Format in Default Mode, RGB_CFG = 00, No Swap Byte 0 Byte 1 Byte 2 R4 i+1 R3 i+1 R2 i+1 R1 i+1 Byte 3 G2 i+1 G1 i+1 G0 i+1 B4 i+1 R0 i B3 i R0 i+1 B3 i+1 G5 i B2 i G5 i+1 B2 i+1 G4 i B1 i G4 i+1 B1 i+1 G3 i B0 i G3 i+1 B0 i+1 Table Mode RGB 5:6:5 RGB Format, RGB_CFG = 10 Mode 2 , No Swap Byte Byte 0 Byte 1 Byte 2 G2 i+1 G1 i+1 G0 i+1 R4 i+1 Byte 3 B4 i+1 B3 i+1 B2 i+1 B1 i+1 This block serializes the data read from memory. It reads words from the FIFO and outputs pixels 1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide depending on the format specified in the PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both bigendian and little-endian formats are supported. They are configured in the MEMOR field of the LCDCON2 register. The organization of the pixel data in the memory depends on the configuration and is shown in Table 45-5 and Table Note: For a color depth of 24 bits per pixel there are two different formats supported packed and unpacked. The packed format needs less memory but has some limitations when working in 2D addressing mode See “2D Memory Addressing” on page 1048 AT91SAM9G45 AT91SAM9G45 Table Little Endian Memory Organization Mem Addr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixel 1bpp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixel 2bpp 15 Pixel 4bpp Pixel 8bpp Pixel 16bpp Pixel 24bpp packed Pixel 24bpp packed Pixel 24bpp packed Pixel 24bpp not used unpacked Table Big Endian Memory Organization Mem Addr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixel 1bpp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pixel 2bpp 0 Pixel 4bpp Pixel 8bpp Pixel 16bpp Pixel 24bpp packed Pixel 24bpp packed • PIXELOFF DAM2D Addressing Pixel offset When 2D DMA addressing is enabled bit DMA2DEN is set in register DMACON , this field specifies the offset of the first pixel in each line within the memory word that contains this pixel. The offset is specified in number of bits in the range 0-31, so for example a value of 4 indicates that the first pixel in the screen starts at bit 4 of the 32-bit word pointed by register DMABADDR1. Bits 0 to 3 of that word are not used. This example is valid for little endian memory organization. When using big endian memory organization, this offset is considered from bit 31 downwards, or equivalently, a given value of this field always selects the pixel in the same relative position within the word, independently of the memory ordering configuration. Bit DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the DMA controller use this new value. 1078 AT91SAM9G45 AT91SAM9G45 LCD Control Register 1 Name LCDCON1 Address:0x00500800 Access Read-write, except LINECNT Read-only Reset value 0x00002000 LINECNT CLKVAL LINECNT CLKVAL • BYPASS LCDDOTCK Divider 0 The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field. 1 The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency. • CLKVAL Clock Divider 9-bit divider for pixel clock LCDDOTCK frequency. Pixel_clock = system_clock CLKVAL + 1 • LINECNT Line Counter Read-only Current Value of 11-bit line counter. Down count from LINEVAL to 8 0 BYPASS 1079 LCD Control Register 2 Name LCDCON2 Address:0x00500804 Access Read-write Reset value: MEMOR CLKMOD PIXELSIZE INVDVAL INVCLK IFWIDTH 26 18 10 INVLINE 2 SCANMOD INVFRAME INVVD DISTYPE • DISTYPE Display Type DISTYPE STN Monochrome STN Color TFT Reserved • SCANMOD Scan Mode 0 Single Scan 1 Dual Scan • IFWIDTH Interface width STN IFWIDTH 4-bit Only valid in single scan STN mono or color 8-bit Only valid in STN mono or Color 16-bit Only valid in dual scan STN mono or color Reserved 1080 AT91SAM9G45 • MEMOR Memory Ordering Format 00 Big Endian 10 Little Endian 11 WinCE format AT91SAM9G45 1081 LCD Timing Configuration Register 1 Name LCDTIM1 Address:0x00500808 Access Read-write Reset value: VHDLY • VFP Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to • VBP Vertical Back Porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame. In STN mode, these bits should be set to • VPW Vertical Synchronization pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. LCDVSYNC width is equal to VPW+1 lines. In STN mode, these bits should be set to • VHDLY Vertical to horizontal delay In TFT mode, this is the delay between LCDVSYNC rising or falling edge and LCDHSYNC rising edge. Delay is VHDLY+1 LCDDOTCK cycles. Bit 31 must be written to In STN mode, these bits should be set to 1082 AT91SAM9G45 AT91SAM9G45 LCD Timing Configuration Register 2 Name LCDTIM2 Address:0x0050080C Access Read-write Reset value: • HBP Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is HBP+1 LCDDOTCK cycles. • HPW Horizontal synchronization pulse width of the LCDHSYNC pulse, given in LCDDOTCK cycles. Width is HPW+1 LCDDOTCK cycles. • HFP Horizontal Front Porch Number of idle LCDDOTCK cycles at the end of the line. Idle period is HFP+1 LCDDOTCK cycles. 1083 LCD Frame Configuration Register Name LCDFRMCFG Address:0x00500810 Access Read-write Reset value: LINESIZE LINESIZE LINEVAL LINEVAL • LINEVAL Vertical size of LCD module In single scan mode vertical size of LCD Module, in pixels, minus 1 In dual scan mode vertical display size of each LCD panel, in pixels, minus 1 • LINESIZE Horizontal size of LCD module, in pixels, minus 1 1084 AT91SAM9G45 AT91SAM9G45 LCD FIFO Register Name LCDFIFO Address:0x00500814 AT91SAM9G45 Ordering Information Table AT91SAM9G45 Ordering Information Ordering Code Package AT91SAM9G45-CU TFBGA324 Package Type Green Temperature Operating Range Industrial -40°C to 85°C 1136 AT91SAM9G45 AT91SAM9G45 AT91SAM9G45 Errata Marking All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats: YYWW V where Errata on engineering samples of the AT91SAM9G45 is available at 1137 Errata Error Corrected Code Controller ECC ECC Computation with a 1 clock cycle long NRD/NWE pulse If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, HECC can't compute the parity. Problem/Fix Workaround It is recommended to program SMC with a value superior to Pulse Width Modulation Controller PWM PWM Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register. Problem/Fix Workaround None Serial Synchronous Controller SSC SSC Data sent without any frame synchro When SSC is configured with the following conditions: • RF is in input, • TD is synchronized on a receive START any condition START field = 2 to 7 • TF toggles at each start of data transfer • Transmit STTDLY = 0 • Check TD and TF after a receive START, The data is sent but there is not any toggle of the TF line Problem/Fix Workaround Transmit STTDLY must be different from SSC Unexpected delay on TD output When SSC is configured with the following conditions: • TCMR.STTDLY more than 0 • RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge • RFMR.FSOS = None input • TCMR.START = Receive Start Unexpected delay of 2 or 3 system clock cycles is added to TD output. Problem/Fix Workaround None 1138 AT91SAM9G45 AT91SAM9G45 In the tables that follow, the most recent version appears first. Comments Introduction “Two Three-channel 32-bit Timer/Counters” peripheral feature changed into “Two Three-channel 16-bit Timer/Counters” ECC row added to Figure 6-1 “AT91SAM9G45 Memory Mapping” Typos corrected in Table 8-1 AC97 --> AC97C also in Table 24-1 and Table 41-1 , PWMC --> PWM, RNG --> TRNG also in Figure 2-1 and Table 46-4 Bus Matrix Figure 19-1 “DDR Multi-port”, and text above and below added. 1 row and 1 column added to Table 19-3 and Table DDR/SDR SDRAM Controller DDRSDRC “NO_OPTI” bit removed. “DIS_ANTICIP_READ” description edited. Electrical Characteristics Section “DDR2SDRC Timings”, list of Supported speed grade limitations updated. Section “Touch Screen ADC TSADC ”, TTH ns formula edited. Last sentence in the Note added. Table 46-2 ‘DC Characteristics’, ISC values changed. Ethernet MAC 10/100 EMAC Wake-on-LAN feature activated, including Section “Wake-on-LAN Support” and Section “Wake-on-LAN Register”. EMAC interrupt on Wake-on-LAN Event activated. Peripheral DMA Controller PDC Typos corrected in Table 24-1 AC97 --> AC97C and TSDAC --> TSADCC Power Management Controller PMC Section “PMC Programmable Clock Register”, CSS and SLCMCK fields edited. Universal Synchronous Asynchronous Receiver Transmitter USART Section “Universal Synchronous Asynchronous Receiver Transmitter USART ”, SPI feature added. Change Request Ref. 6828 6842 RFO 6797 6871 6776 6800 RFO 6847 6872 6903 6836 6838 RFO 48 AT91SAM9G45 Ordering Information 1136 49 AT91SAM9G45 Errata 1137 Marking Errata Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581 Product Contact Web Site Literature Requests Technical Support AT91SAM Support Atmel technical support Sales Contacts Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. 2009 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. and the ARMPowered and others, are registered trademarks or trademarks of ARM Ltd. and others, are registered trademarks or trademarks of Microsoft Corporation in the US and/or other countries. Other terms and product names may be trademarks of others.

PDF Datasheet Preview

• 400 MHz ARM926EJ-S Processor 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU
• Memories DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC One 64-KByte internal SRAM, single-cycle access at system speed or processor speed through TCM interface One 64-KByte internal ROM, embedding bootstrap routine
• Peripherals LCD Controller supporting STN and TFT displays up to 1280*860 ITU-R BT. 601/656 Image Sensor Interface USB Device High Speed, USB Host High Speed and USB Host Full Speed with OnChip Transceiver 10/100 Mbps Ethernet MAC Controller Two High Speed Memory Card Hosts SDIO, SDCard, MMC AC'97 controller Two Master/Slave Serial Peripheral Interfaces Two Three-channel 16-bit Timer/Counters Two Synchronous Serial Controllers I2S mode Four-channel 16-bit PWM Controller Two-wire Interfaces Four USARTs with ISO7816, IrDA, Manchester and SPI modes 8-channel 10-bit ADC with 4-wire Touch Screen support
• System 133 MHz twelve 32-bit layer AHB Bus Matrix 37 DMA Channels Boot from NAND Flash, SDCard, or serial DataFlash Reset Controller with on-chip Power-on Reset Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators Internal Low-power 32 kHz RC Oscillator One PLL for the system and one 480 MHz PLL optimized for USB High Speed Two Programmable External Clock Signals Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock
• I/O Five 32-bit Parallel Input/Output Controllers 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input
• Package 324-ball TFBGA, pitch mm

AT91 ARM Thumb-based Microcontrollers

AT91SAM9G45

The ARM926EJ-S based AT91SAM9G45 features the frequently demanded combination of user interface functionality and high data rate connectivity, including LCD Controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the processor running at 400MHz and multiple 100+ Mbps data rate peripherals, the AT91SAM9G45 has the performance and bandwidth to the network or local storage media to provide an adequate user experience.

The AT91SAM9G45 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and distributed memory including a 64KByte SRAM which can be configured as a tightly coupled memory TCM sustains the high bandwidth required by the processor and the high speed peripherals.

The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports ball pitch package for low cost PCB manufacturing.

The AT91SAM9G45 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes.
2 AT91SAM9G45

NTRST TTTTCDDMIKSO RTCK JTAGSEL BMS VHHFBHSGSDDPPAA,,HHFHSSDDMMAA

Block Diagram

Figure AT91SAM9G45 Block Diagram

TST PCK0-PCK1

FIQ IRQ DRXD DTXD

XIN XOUT

XIN32 XOUT32

SHDN WKUP VDDBU NRST VDDCORE

System Controller

JTAG / Boundary Scan

HS Transceiver

HS Transceiver

DBGU

PLLA PLLUTMI OSC12M

RC OSC 32K SHDC
4 GPBR RTT

RSTC

PIOA PIOB PIOC

PIOD PIOE

In-Circuit Emulator

ARM926EJ-S

ICache

DCache
32 Kbytes MMU 32 Kbytes

ITCM DTCM Bus Interface

PA PB

HS EHCI USB HOST

SRAM 64KB
Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding.

All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format.

Table Mode Default Mode1 Mode2 Mode3
Data Ordering in YCbCr Mode

Byte 0

Byte 1

Byte 2 Cr i Cb i Y i+1 Y i+1

Byte 3 Y i+1 Y i+1 Cr i Cb i

Table Mode

RGB 8:8:8

RGB Format in Default Mode, RGB_CFG = 00, No Swap

Byte

Byte 0

Byte 1

Byte 2

Byte 3

R7 i+1 R6 i+1 R5 i+1 R4 i+1

D3 R3 i G3 i B3 i R3 i+1

D2 R2 i G2 i B2 i R2 i+1

D1 R1 i G1 i B1 i R1 i+1

D0 R0 i G0 i B0 i R0 i+1

AT91SAM9G45

Table RGB 5:6:5

RGB Format in Default Mode, RGB_CFG = 00, No Swap

Byte 0

Byte 1

Byte 2

R4 i+1 R3 i+1 R2 i+1 R1 i+1

Byte 3

G2 i+1 G1 i+1 G0 i+1 B4 i+1

R0 i B3 i R0 i+1 B3 i+1

G5 i B2 i G5 i+1 B2 i+1

G4 i B1 i G4 i+1 B1 i+1

G3 i B0 i G3 i+1 B0 i+1

Table Mode

RGB 5:6:5

RGB Format, RGB_CFG = 10 Mode 2 , No Swap

Byte

Byte 0

Byte 1

Byte 2

G2 i+1 G1 i+1 G0 i+1 R4 i+1

Byte 3

B4 i+1 B3 i+1 B2 i+1 B1 i+1
This block serializes the data read from memory. It reads words from the FIFO and outputs pixels 1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide depending on the format specified in the PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both bigendian and little-endian formats are supported. They are configured in the MEMOR field of the LCDCON2 register.

The organization of the pixel data in the memory depends on the configuration and is shown in Table 45-5 and Table

Note:

For a color depth of 24 bits per pixel there are two different formats supported packed and unpacked. The packed format needs less memory but has some limitations when working in 2D addressing mode See “2D Memory Addressing” on page
1048 AT91SAM9G45

AT91SAM9G45

Table Little Endian Memory Organization

Mem Addr

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Pixel 1bpp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Pixel 2bpp 15

Pixel 4bpp

Pixel 8bpp

Pixel 16bpp

Pixel
24bpp
packed

Pixel
24bpp
packed

Pixel
24bpp
packed

Pixel
24bpp
not used
unpacked

Table Big Endian Memory Organization

Mem Addr

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Pixel 1bpp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Pixel 2bpp 0

Pixel 4bpp

Pixel 8bpp

Pixel 16bpp

Pixel
24bpp
packed

Pixel
24bpp
packed
• PIXELOFF DAM2D Addressing Pixel offset When 2D DMA addressing is enabled bit DMA2DEN is set in register DMACON , this field specifies the offset of the first pixel in each line within the memory word that contains this pixel. The offset is specified in number of bits in the range 0-31, so for example a value of 4 indicates that the first pixel in the screen starts at bit 4 of the 32-bit word pointed by register DMABADDR1. Bits 0 to 3 of that word are not used. This example is valid for little endian memory organization. When using big endian memory organization, this offset is considered from bit 31 downwards, or equivalently, a given value of this field always selects the pixel in the same relative position within the word, independently of the memory ordering configuration. Bit DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the DMA controller use this new value.
1078 AT91SAM9G45

AT91SAM9G45

LCD Control Register 1 Name LCDCON1

Address:0x00500800

Access Read-write, except LINECNT Read-only

Reset value 0x00002000

LINECNT

CLKVAL

LINECNT

CLKVAL
• BYPASS LCDDOTCK Divider 0 The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field.
1 The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency.
• CLKVAL Clock Divider 9-bit divider for pixel clock LCDDOTCK frequency.

Pixel_clock = system_clock CLKVAL + 1
• LINECNT Line Counter Read-only Current Value of 11-bit line counter. Down count from LINEVAL to
8 0 BYPASS
1079

LCD Control Register 2 Name LCDCON2

Address:0x00500804

Access Read-write

Reset value:

MEMOR

CLKMOD

PIXELSIZE

INVDVAL

INVCLK

IFWIDTH
26 18 10 INVLINE 2 SCANMOD

INVFRAME

INVVD

DISTYPE
• DISTYPE Display Type

DISTYPE

STN Monochrome STN Color TFT Reserved
• SCANMOD Scan Mode 0 Single Scan
1 Dual Scan
• IFWIDTH Interface width STN

IFWIDTH
4-bit Only valid in single scan STN mono or color 8-bit Only valid in STN mono or Color 16-bit Only valid in dual scan STN mono or color Reserved
1080 AT91SAM9G45
• MEMOR Memory Ordering Format 00 Big Endian 10 Little Endian 11 WinCE format

AT91SAM9G45
1081

LCD Timing Configuration Register 1 Name LCDTIM1

Address:0x00500808

Access Read-write

Reset value:

VHDLY
• VFP Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame.

In STN mode, these bits should be set to
• VBP Vertical Back Porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame.

In STN mode, these bits should be set to
• VPW Vertical Synchronization pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. LCDVSYNC width is equal to VPW+1 lines.

In STN mode, these bits should be set to
• VHDLY Vertical to horizontal delay In TFT mode, this is the delay between LCDVSYNC rising or falling edge and LCDHSYNC rising edge. Delay is VHDLY+1 LCDDOTCK cycles. Bit 31 must be written to

In STN mode, these bits should be set to
1082 AT91SAM9G45

AT91SAM9G45

LCD Timing Configuration Register 2 Name LCDTIM2

Address:0x0050080C

Access Read-write

Reset value:
• HBP Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is HBP+1 LCDDOTCK cycles.
• HPW Horizontal synchronization pulse width of the LCDHSYNC pulse, given in LCDDOTCK cycles. Width is HPW+1 LCDDOTCK cycles.
• HFP Horizontal Front Porch Number of idle LCDDOTCK cycles at the end of the line. Idle period is HFP+1 LCDDOTCK cycles.
1083

LCD Frame Configuration Register Name LCDFRMCFG

Address:0x00500810

Access Read-write

Reset value:

LINESIZE

LINESIZE

LINEVAL

LINEVAL
• LINEVAL Vertical size of LCD module In single scan mode vertical size of LCD Module, in pixels, minus 1

In dual scan mode vertical display size of each LCD panel, in pixels, minus 1
• LINESIZE Horizontal size of LCD module, in pixels, minus 1
1084 AT91SAM9G45

AT91SAM9G45

LCD FIFO Register Name LCDFIFO

Address:0x00500814
AT91SAM9G45 Ordering Information
Table AT91SAM9G45 Ordering Information
Ordering Code

Package

AT91SAM9G45-CU

TFBGA324

Package Type Green

Temperature Operating Range

Industrial -40°C to 85°C
1136 AT91SAM9G45

AT91SAM9G45

AT91SAM9G45 Errata

Marking
All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats:

YYWW V
where

Errata on engineering samples of the AT91SAM9G45 is available at
1137

Errata

Error Corrected Code Controller ECC

ECC Computation with a 1 clock cycle long NRD/NWE pulse If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, HECC can't compute the parity.

Problem/Fix Workaround It is recommended to program SMC with a value superior to

Pulse Width Modulation Controller PWM

PWM Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register.

Problem/Fix Workaround None

Serial Synchronous Controller SSC

SSC Data sent without any frame synchro When SSC is configured with the following conditions:
• RF is in input,
• TD is synchronized on a receive START any condition START field = 2 to 7
• TF toggles at each start of data transfer
• Transmit STTDLY = 0
• Check TD and TF after a receive START, The data is sent but there is not any toggle of the TF line

Problem/Fix Workaround Transmit STTDLY must be different from

SSC Unexpected delay on TD output When SSC is configured with the following conditions:
• TCMR.STTDLY more than 0
• RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge
• RFMR.FSOS = None input
• TCMR.START = Receive Start Unexpected delay of 2 or 3 system clock cycles is added to TD output.

Problem/Fix Workaround None
1138 AT91SAM9G45

AT91SAM9G45

In the tables that follow, the most recent version appears first.

Comments

Introduction “Two Three-channel 32-bit Timer/Counters” peripheral feature changed into “Two Three-channel 16-bit Timer/Counters”

ECC row added to Figure 6-1 “AT91SAM9G45 Memory Mapping”

Typos corrected in Table 8-1 AC97 --> AC97C also in Table 24-1 and Table 41-1 , PWMC --> PWM, RNG --> TRNG also in Figure 2-1 and Table 46-4

Bus Matrix Figure 19-1 “DDR Multi-port”, and text above and below added. 1 row and 1 column added to Table 19-3 and Table

DDR/SDR SDRAM Controller DDRSDRC “NO_OPTI” bit removed. “DIS_ANTICIP_READ” description edited.

Electrical Characteristics Section “DDR2SDRC Timings”, list of Supported speed grade limitations updated.

Section “Touch Screen ADC TSADC ”, TTH ns formula edited. Last sentence in the Note added.

Table 46-2 ‘DC Characteristics’, ISC values changed.

Ethernet MAC 10/100 EMAC Wake-on-LAN feature activated, including Section “Wake-on-LAN Support” and Section “Wake-on-LAN Register”. EMAC interrupt on Wake-on-LAN Event activated.

Peripheral DMA Controller PDC Typos corrected in Table 24-1 AC97 --> AC97C and TSDAC --> TSADCC

Power Management Controller PMC Section “PMC Programmable Clock Register”, CSS and SLCMCK fields edited.

Universal Synchronous Asynchronous Receiver Transmitter USART Section “Universal Synchronous Asynchronous Receiver Transmitter USART ”, SPI feature added.

Change Request Ref.
6828 6842 RFO
6797
6871
6776 6800 RFO 6847 6872 6903
6836 6838 RFO
48 AT91SAM9G45 Ordering Information 1136 49 AT91SAM9G45 Errata 1137

Marking Errata

Headquarters

Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel 1 408 441-0311 Fax 1 408 487-2600

International

Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel 852 2245-6100 Fax 852 2722-1369

Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel 33 1-30-60-70-00 Fax 33 1-30-60-71-11

Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581

Product Contact

Web Site

Literature Requests

Technical Support AT91SAM Support Atmel technical support

Sales Contacts

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
2009 Atmel Corporation. All rights reserved. Atmel logo and combinations thereof, and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. and the ARMPowered and others, are registered trademarks or trademarks of ARM Ltd. and others, are registered trademarks or trademarks of Microsoft Corporation in the US and/or other countries. Other terms and product names may be trademarks of others.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT91SAM9G45-EKES Datasheet file may be downloaded here without warranties.

Datasheet ID: AT91SAM9G45-EKES 519140