74F164ASJ

74F164ASJ Datasheet

74F164A Serial-In, Parallel-Out Shift Register

Part	Datasheet
74F164ASJ	74F164ASJ (pdf)

Related Parts	Information
74F164ASCX	74F164ASCX
74F164ASC	74F164ASC
74F164APC	74F164APC
74F164ASJX	74F164ASJX

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74F164A Serial-In, Parallel-Out Shift Register 74F164A Serial-In, Parallel-Out Shift Register The 74F164A is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent of the clock. The 74F164A is a faster version of the 74F164. s Typical shift frequency of 90 MHz s Asynchronous Master Reset s Gated serial data input s Fully synchronous data transfers s 74F164A is a faster version of the 74F164 Ordering Code: Order Number Package Number Package Description 74F164ASC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow 74F164ASJ M14D 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F164APC N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS010613 74F164A Unit Loading/Fan Out Pin Names A, B CP MR Data Inputs Clock Pulse Input Active Rising Edge Master Reset Input Active LOW Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Functional Description The 74F164A is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs A or B either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH. Each LOW-to-HIGH transition on the Clock CP input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs A • B that existed before the rising clock edge. A LOW level on the Master Reset MR input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW. Mode Select Table Operating Inputs Outputs Mode MR A B Q0 Reset Clear L X L Shift H l h L H = HIGH Voltage Levels L = LOW Voltage Levels X = Immaterial qn = Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F164A Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 1 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 1 −30 mA to mA Voltage Applied to Output

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74F164A Serial-In, Parallel-Out Shift Register
74F164A Serial-In, Parallel-Out Shift Register

The 74F164A is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through a 2-input AND gate synchronous with the LOW-to-HIGH transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs LOW independent of the clock. The 74F164A is a faster version of the 74F164.
s Typical shift frequency of 90 MHz s Asynchronous Master Reset s Gated serial data input s Fully synchronous data transfers s 74F164A is a faster version of the 74F164
Ordering Code:

Order Number Package Number

Package Description
74F164ASC

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow
74F164ASJ

M14D
14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F164APC

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS010613
74F164A

Unit Loading/Fan Out

Pin Names

A, B CP MR

Data Inputs Clock Pulse Input Active Rising Edge Master Reset Input Active LOW Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA

Functional Description

The 74F164A is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs A or B either of these inputs can be used as an active HIGH Enable for data entry through the other input. An unused input must be tied HIGH.

Each LOW-to-HIGH transition on the Clock CP input shifts data one place to the right and enters into Q0 the logical AND of the two data inputs A
• B that existed before the rising clock edge. A LOW level on the Master Reset MR input overrides all other inputs and clears the register asynchronously, forcing all Q outputs LOW.

Mode Select Table

Operating

Inputs

Outputs

Mode

MR A B Q0

Reset Clear L X L

Shift

H l h L

H = HIGH Voltage Levels L = LOW Voltage Levels X = Immaterial qn = Lower case letters indicate the state of the referenced input or output
one setup time prior to the LOW-to-HIGH clock transition.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F164A

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 1
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 1
−30 mA to mA

Voltage Applied to Output

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Datasheet ID: 74F164ASJ 513286