74F160APC

74F160APC Datasheet

74F160A<br>• 74F162A Synchronous Presettable BCD Decade Counter

Part	Datasheet
74F160APC	74F160APC (pdf)

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74F160A • 74F162A Synchronous Presettable BCD Decade Counter 74F160A • 74F162A Synchronous Presettable BCD Decade Counter The 74F160A and 74F162A are high-speed synchronous decade counters operating in the BCD 8421 sequence. They are synchronously presettable for applications in programmable dividers. There are two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The F160A has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The F162A has a Synchronous Reset input that overrides counting and parallel loading and allows all outputs to be simultaneously reset on the rising edge of the clock. The F160A and F162A are high speed versions of the F160 and F162. s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 120 MHz Ordering Code: Order Number Package Number Package Description 74F160ASC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F160ASJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F160APC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74F162ASC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F162APC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74F160A 74F162A 1999 Fairchild Semiconductor Corporation DS009485 74F160A • 74F162A Logic Symbols 74F160A IEEE/IEC 74F162A 74F160A Unit Loading/Fan Out 74F162A Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL Count Enable Parallel Input 20 µA/−0.6 mA Count Enable Trickle Input 20 µA/−1.2 mA Clock Pulse Input Active Rising Edge 20 µA/−0.6 mA MR 74F160A Asynchronous Master Reset Input Active LOW 20 µA/−0.6 mA SR 74F162A Synchronous Reset Input Active LOW 20 µA/−1.2 mA Parallel Data Inputs Parallel Enable Input Active LOW 20 µA/−0.6 mA 20 µA/−1.2 mA Flip-Flop Outputs Terminal Count Output −1 mA/20 mA −1 mA/20 mA 74F160A • 74F162A Functional Description The 74F160A and 74F162A count modulo-10 in the BCD 8421 sequence. From state 9 HLLH they increment to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs except due to Master Reset of the F160A occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence asynchronous reset F160A , synchronous reset F162A , parallel load, count-up and hold. Five control Reset MR, F160A , Synchronous Reset SR, F162A , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR F160A or SR F162A HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The F160A and F162A use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count TC output is HIGH when CET is HIGH and counter is in state To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the F160A and F162A decade counters, the TC output is fully decoded and can only be HIGH in state If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the State Diagram. Logic Equations: Count Enable = CEP x CET x PE TC = Q0 x Q 1x Q 2 x Q3 x CET Mode Select Table SR PE CET CEP LXXX HLXX HHHH HHL X HHX L For 74’F162A only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

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74F160A
• 74F162A Synchronous Presettable BCD Decade Counter
74F160A
• 74F162A Synchronous Presettable BCD Decade Counter

The 74F160A and 74F162A are high-speed synchronous decade counters operating in the BCD 8421 sequence. They are synchronously presettable for applications in programmable dividers. There are two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The F160A has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The F162A has a Synchronous Reset input that overrides counting and parallel loading and allows all outputs to be simultaneously reset on the rising edge of the clock. The F160A and F162A are high speed versions of the F160 and F162.
s Synchronous counting and loading s High-speed synchronous expansion s Typical count rate of 120 MHz
Ordering Code:

Order Number Package Number

Package Description
74F160ASC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F160ASJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F160APC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74F162ASC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F162APC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams
74F160A
74F162A
1999 Fairchild Semiconductor Corporation DS009485
74F160A
• 74F162A

Logic Symbols
74F160A IEEE/IEC
74F162A
74F160A

Unit Loading/Fan Out
74F162A

Pin Names

U.L.

Input IIH/IIL

HIGH/LOW Output IOH/IOL

Count Enable Parallel Input
20 µA/−0.6 mA

Count Enable Trickle Input
20 µA/−1.2 mA

Clock Pulse Input Active Rising Edge
20 µA/−0.6 mA

MR 74F160A Asynchronous Master Reset Input Active LOW 20 µA/−0.6 mA

SR 74F162A Synchronous Reset Input Active LOW
20 µA/−1.2 mA

Parallel Data Inputs Parallel Enable Input Active LOW
20 µA/−0.6 mA 20 µA/−1.2 mA

Flip-Flop Outputs Terminal Count Output
−1 mA/20 mA −1 mA/20 mA
74F160A
• 74F162A

Functional Description

The 74F160A and 74F162A count modulo-10 in the BCD 8421 sequence. From state 9 HLLH they increment to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs except due to Master Reset of the F160A occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence asynchronous reset F160A , synchronous reset F162A , parallel load, count-up and hold. Five control Reset MR, F160A , Synchronous Reset SR, F162A , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR F160A or SR F162A HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.

The F160A and F162A use D-type edge-triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.

The Terminal Count TC output is HIGH when CET is HIGH and counter is in state To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. In the F160A and F162A decade counters, the TC output is fully decoded and can only be HIGH in state If a decade counter is preset to an illegal state, or assumes an illegal state when power is applied, it will return to the normal sequence within two counts, as shown in the State Diagram.

Logic Equations:

Count Enable = CEP x CET x PE

TC = Q0 x Q 1x Q 2 x Q3 x CET

Mode Select Table
*SR PE CET CEP

LXXX HLXX HHHH HHL X HHX L
*For 74’F162A only H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

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Datasheet ID: 74F160APC 513282