74F114PC

74F114PC Datasheet

74F114 Dual JK Negative Edge-Triggered Flip-Flop

Part	Datasheet
74F114PC	74F114PC (pdf)

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74F114 Dual JK Negative Edge-Triggered Flip-Flop 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of Clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74F114SC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow 74F114PC N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 1999 Fairchild Semiconductor Corporation DS009474 74F114 Unit Loading/Fan Out Pin Names J1, J2, K1, K2 CP Data Inputs Clock Pulse Input Active Falling Edge CD SD1, SD2 Q1, Q2, Q1, Q2 Direct Clear Input Active LOW Direct Set Inputs Active LOW Outputs U.L. HIGH/LOW Truth Table Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−4.8 mA 20 µA/−6.0 mA 20 µA/−3.0 mA −1 mA/20 mA Inputs Outputs H = HIGH Voltage Level L h = LOW Voltage Level = Immaterial = HIGH-to-LOW Clock Transition Q0 = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. Logic Diagram one half shown Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F114 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA

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74F114 Dual JK Negative Edge-Triggered Flip-Flop
74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

The 74F114 contains two high-speed JK flip-flops with common Clock and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively.

Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs:

LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of Clock Simultaneous LOW on CD and SD
makes both Q and Q HIGH
Ordering Code:

Order Number Package Number

Package Description
74F114SC

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow
74F114PC

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
1999 Fairchild Semiconductor Corporation DS009474
74F114

Unit Loading/Fan Out

Pin Names

J1, J2, K1, K2 CP

Data Inputs Clock Pulse Input Active Falling Edge

CD SD1, SD2 Q1, Q2, Q1, Q2

Direct Clear Input Active LOW Direct Set Inputs Active LOW Outputs

U.L. HIGH/LOW

Truth Table

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−4.8 mA 20 µA/−6.0 mA 20 µA/−3.0 mA −1 mA/20 mA

Inputs

Outputs

H = HIGH Voltage Level L h = LOW Voltage Level
= Immaterial = HIGH-to-LOW Clock Transition Q0 = Before HIGH-to-LOW Transition of Clock

Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition.

Logic Diagram
one half shown

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F114

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

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Datasheet ID: 74F114PC 513270