74F109SJ

74F109SJ Datasheet

74F109 Dual JK Positive Edge-Triggered Flip-Flop

Part	Datasheet
74F109SJ	74F109SJ (pdf)

Related Parts	Information
74F109SJX	74F109SJX
74F109SC	74F109SC
74F109SCX	74F109SCX
74F109PC	74F109PC

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74F109 Dual JK Positive Edge-Triggered Flip-Flop 74F109 Dual JK Positive Edge-Triggered Flip-Flop The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop refer to F74 data sheet by connecting the J and K inputs. Asynchronous Inputs LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74F109SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F109SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F109PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009471 74F109 Truth Table Inputs Outputs X I h I h Toggle H = HIGH Voltage Level l = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0 = Before LOW-to-HIGH Transition of Clock Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition. Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL J1, J2, K1, K2 Data Inputs CP1, CP2 Clock Pulse Inputs Active Rising Edge CD1, CD2 Direct Clear Inputs Active LOW SD1, SD2 Direct Set Inputs Active LOW Q1, Q2, Q1, Q2 Outputs 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.8 mA 20 µA/−1.8 mA −1 mA/20 mA Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F109 Absolute Maximum Ratings Note 1 Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Output in HIGH State with Vcc = 0V Standard Output 3-STATE Output Current Applied to Output in LOW State Max −65°C to +150°C −55°C to +125°C −55°C to +175°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to mA −0.5V to VCC −0.5V to +5.5V twice the rated IOL mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V

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74F109 Dual JK Positive Edge-Triggered Flip-Flop
74F109 Dual JK Positive Edge-Triggered Flip-Flop

The F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-type flip-flop refer to F74 data sheet by connecting the J and K inputs.

Asynchronous Inputs LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
Ordering Code:

Order Number Package Number

Package Description
74F109SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F109SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F109PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009471
74F109

Truth Table

Inputs

Outputs

X I h I h

Toggle

H = HIGH Voltage Level
l = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0 = Before LOW-to-HIGH Transition of Clock

Lower case letters indicate the state of the referenced output one setup time prior to the LOW-to-HIGH clock transition.

Unit Loading/Fan Out

Pin Names

U.L.

Input IIH/IIL

HIGH/LOW Output IOH/IOL

J1, J2, K1, K2 Data Inputs

CP1, CP2

Clock Pulse Inputs Active Rising Edge

CD1, CD2

Direct Clear Inputs Active LOW

SD1, SD2

Direct Set Inputs Active LOW

Q1, Q2, Q1, Q2 Outputs
20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.8 mA 20 µA/−1.8 mA −1 mA/20 mA

Block Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F109

Absolute Maximum Ratings Note 1

Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to

Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Output in HIGH State with Vcc = 0V

Standard Output 3-STATE Output Current Applied to Output in LOW State Max
−65°C to +150°C −55°C to +125°C −55°C to +175°C
−0.5V to +7.0V −0.5V to +7.0V −30 mA to mA
−0.5V to VCC −0.5V to +5.5V
twice the rated IOL mA

Recommended Operating Conditions

Free Air Ambient Temperature Supply Voltage
0°C to +70°C +4.5V to +5.5V

More datasheets: FW250H1 | FW300H1 | DFR0468 | 74F175SJ | 74F175SCX | 74F175SJX | 74F175SC | 74F175PC | 19039732A | 74F109SJX

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Datasheet ID: 74F109SJ 513265