74ALVCH162244TX

74ALVCH162244TX Datasheet

74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and Series Resistor in Outputs

Part	Datasheet
74ALVCH162244TX	74ALVCH162244TX (pdf)

Related Parts	Information
74ALVCH162244T	74ALVCH162244T

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74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and Series Resistor in Outputs 74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and Series Resistor in Outputs The ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble 4-bit controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ALVCH162244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level The 74ALVCH162244 is also designed with series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74ALVCH162244 is designed for low voltage 1.65V to 3.6V VCC applications with output capability up to 3.6V. The 74ALVCH162244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s series resistors in outputs s tPD ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V Ordering Code: Order Number Package Number Package Description 74ALVCH162244T MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description Output Enable Input Active LOW Bushold Inputs Outputs 2002 Fairchild Semiconductor Corporation DS500632 74ALVCH162244 Connection Diagram Truth Tables Inputs OE1 L H Outputs Inputs OE2 L H Outputs Inputs OE3 L H Outputs Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance Functional Description The 74ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable OEn input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. Logic Diagram 74ALVCH162244 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 2 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 3 Power Supply Operating 1.65V to 3.6V Input Voltage Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate

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74ALVCH162244 Low Voltage 16-Bit Buffer/Line Driver with Bushold and Series Resistor in Outputs
74ALVCH162244

Low Voltage 16-Bit Buffer/Line Driver with Bushold and Series Resistor in Outputs

The ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble 4-bit controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.

The ALVCH162244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level

The 74ALVCH162244 is also designed with series resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.

The 74ALVCH162244 is designed for low voltage 1.65V to 3.6V VCC applications with output capability up to 3.6V.

The 74ALVCH162244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors s series resistors in outputs s tPD
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V
Ordering Code:

Order Number

Package Number

Package Description
74ALVCH162244T

MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

Description Output Enable Input Active LOW Bushold Inputs Outputs
2002 Fairchild Semiconductor Corporation DS500632
74ALVCH162244

Connection Diagram

Truth Tables

Inputs

OE1 L H

Outputs

Inputs OE2 L H

Outputs

Inputs OE3 L H

Outputs

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance

Functional Description

The 74ALVCH162244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE outputs are controlled by an Output Enable OEn input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs.

Logic Diagram
74ALVCH162244

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 2 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to 4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 3

Power Supply

Operating
1.65V to 3.6V

Input Voltage

Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate

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Datasheet ID: 74ALVCH162244TX 513249