74ALVC16827MTD

74ALVC16827MTD Datasheet


74ALVC16827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

Part Datasheet
74ALVC16827MTD 74ALVC16827MTD 74ALVC16827MTD (pdf)
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74ALVC16827MTDX 74ALVC16827MTDX 74ALVC16827MTDX
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74ALVC16827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
74ALVC16827 Low Voltage 20-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

The ALVC16827 contains twenty non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver carrying parity. The device is byte controlled. Each byte has NOR output enables for maximum control flexibility.

The 74ALVC16827 is designed for low voltage 1.65V to 3.6V VCC applications with I/O capability up to 3.6V.

The 74ALVC16827 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74ALVC16827MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

Description Output Enable Input Active LOW Inputs Outputs
2001 Fairchild Semiconductor Corporation DS500697
74ALVC16827

Connection Diagram

Truth Tables

Inputs

Outputs

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance

Functional Description

The 74ALVC16827 contains twenty non-inverting buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation. The 3-STATE outputs are controlled by Output Enable OEn inputs. When OE1, and OE2 are LOW, are in the 2-state mode. When either OE1 or OE2 are HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. The same applies for byte two with OE3 and OE4.

Logic Diagrams
74ALVC16827

Absolute Maximum Ratings Note 2

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to 4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 4

Power Supply

Operating
1.65V to 3.6V

Input Voltage VI Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate
0V to VCC 0V to VCC −40°C to +85°C

VIN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V

Note 2 The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 3 IO Absolute Maximum Rating must be observed, limited to 4.6V.

Note 4 Floating or unused control inputs must be held HIGH or LOW.
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Datasheet ID: 74ALVC16827MTD 513242