74ALVC162601T

74ALVC162601T Datasheet

74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and Series Resistors in the B-Port Outputs

Part	Datasheet
74ALVC162601T	74ALVC162601T (pdf)

Related Parts	Information
74ALVC162601TX	74ALVC162601TX

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74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and Series Resistors in the B-Port Outputs 74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and Series Resistors in the B-Port Outputs The 74ALVC162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. The clock can be controlled by the clock-enable CLKENAB and CLKENBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-toLOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. Output-enable OEAB is active-LOW. When OEAB is HIGH, the outputs are in the HIGH-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA. The 74ALVC162601 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V. The 74ALVC162601 is also designed with series resistors in the B-Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. I VCC supply operation I 3.6V tolerant inputs and outputs I series resistors in B-Port outputs I tPD A to B ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC I Power-down high impedance inputs and outputs I Supports live insertion/withdrawal Note 1 I Uses patented noise/EMI reduction circuitry I Latchup conforms to JEDEC JED78 I ESD performance Human body model > 2000V Machine model >200V Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74ALVC162601T MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2001 Fairchild Semiconductor Corporation DS500676 74ALVC162601 Pin Descriptions Connection Diagram Pin Names OEAB, OEBA LEAB, LEBA CLKAB, CLKBA CLKENAB, CLKENBA Output Enable Inputs Active LOW Latch Enable Inputs Clock Inputs Clock Enable Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs Function Table Note 2 Inputs Outputs CLKENAB OEAB LEAB CLKAB An X B0 Note 3 X B0 Note 3 X B0 Note 3 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance B0 Note 4 Note 2 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA. Note 3 Output level before the indicated steady-state input conditions were established. Note 4 Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Logic Diagram 74ALVC162601 Absolute Maximum Ratings Note 5 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 6 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 7 Power Supply

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74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and Series Resistors in the B-Port Outputs
74ALVC162601

Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and Series Resistors in the B-Port Outputs

The 74ALVC162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. The clock can be controlled by the clock-enable CLKENAB and CLKENBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-toLOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. Output-enable OEAB is active-LOW. When OEAB is HIGH, the outputs are in the HIGH-impedance state.

Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.

The 74ALVC162601 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V. The 74ALVC162601 is also designed with series resistors in the B-Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.

I VCC supply operation I 3.6V tolerant inputs and outputs I series resistors in B-Port outputs I tPD A to B
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC I Power-down high impedance inputs and outputs I Supports live insertion/withdrawal Note 1 I Uses patented noise/EMI reduction circuitry I Latchup conforms to JEDEC JED78 I ESD performance Human body model > 2000V Machine model >200V

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number

Package Number

Package Description
74ALVC162601T

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2001 Fairchild Semiconductor Corporation DS500676
74ALVC162601

Pin Descriptions

Connection Diagram

Pin Names OEAB, OEBA

LEAB, LEBA CLKAB, CLKBA CLKENAB, CLKENBA

Output Enable Inputs Active LOW

Latch Enable Inputs

Clock Inputs

Clock Enable Inputs

Side A Inputs or 3-STATE Outputs

Side B Inputs or 3-STATE Outputs

Function Table Note 2

Inputs

Outputs

CLKENAB OEAB LEAB CLKAB An

X B0 Note 3

X B0 Note 3

X B0 Note 3

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance

B0 Note 4

Note 2 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA.

Note 3 Output level before the indicated steady-state input conditions were established.

Note 4 Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.

Logic Diagram
74ALVC162601

Absolute Maximum Ratings Note 5

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 6 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to 4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 7

Power Supply

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Datasheet ID: 74ALVC162601T 513231