74ALVC162373TX

74ALVC162373TX Datasheet

74ALVC162373 Low Voltage 16-Bit Transparent Latch

Part	Datasheet
74ALVC162373TX	74ALVC162373TX (pdf)

Related Parts	Information
74ALVC162373T	74ALVC162373T

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74ALVC162373 Low Voltage 16-Bit Transparent Latch 74ALVC162373 Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and Series Resistors in Outputs The ALVC162373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in a high impedance state. The ALVC162373 is also designed with resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers/transmitters. The 74ALVC162373 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V. The 74ALVC162373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.65V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s series resistors in outputs s tPD In to On ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Support live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Ordering Number Package Number Package Description 74ALVC162373T MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names OEn LEn Description Output Enable Input Active LOW Latch Enable Input Inputs Outputs 2001 Fairchild Semiconductor Corporation DS500709 74ALVC162373 Connection Diagram Truth Tables Inputs Outputs Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of Latch Enable Functional Description The 74ALVC162373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time Logic Diagram its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable OEn input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ALVC162373 Absolute Maximum Ratings Note 2 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 4 Power Supply Operating 1.65V to 3.6V Input Voltage Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate 0V to VCC 0V to VCC −40°C to +85°C

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74ALVC162373 Low Voltage 16-Bit Transparent Latch
74ALVC162373

Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and Series Resistors in Outputs

The ALVC162373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in a high impedance state.

The ALVC162373 is also designed with resistors in the outputs. This design reduces line noise in applications such as memory address drivers, clock drivers and bus transceivers/transmitters.

The 74ALVC162373 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V.

The 74ALVC162373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s series resistors in outputs s tPD In to On
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Support live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Ordering Number Package Number

Package Description
74ALVC162373T

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Pin Names

OEn LEn

Description Output Enable Input Active LOW

Latch Enable Input Inputs Outputs
2001 Fairchild Semiconductor Corporation DS500709
74ALVC162373

Connection Diagram

Truth Tables

Inputs

Outputs

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of Latch Enable

Functional Description

The 74ALVC162373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time

Logic Diagram
its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable OEn input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ALVC162373

Absolute Maximum Ratings Note 2

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to 4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 4

Power Supply

Operating
1.65V to 3.6V

Input Voltage

Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate
0V to VCC 0V to VCC −40°C to +85°C

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Datasheet ID: 74ALVC162373TX 513227