74ACTQ841SPC

74ACTQ841SPC Datasheet

74ACTQ841 Quiet 10-Bit Transparent Latch with 3-STATE Outputs

Part	Datasheet
74ACTQ841SPC	74ACTQ841SPC (pdf)

Related Parts	Information
74ACTQ841SCX	74ACTQ841SCX
74ACTQ841SC	74ACTQ841SC

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74ACTQ841 Quiet 10-Bit Transparent Latch with 3-STATE Outputs 74ACTQ841 Quiet 10-Bit Transparent Latch with 3-STATE Outputs The ACTQ841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 841 is a 10-bit transparent latch, a 10-bit version of the ACTQ841 utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance. s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of package allow easy interface with microprocessors s Improved latch-up immunity s Outputs source/sink 24 mA s Has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACTQ841SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ841SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Descriptions Pin Names OE LE Description Data Inputs 3-STATE Outputs Output Enable Latch Enable Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010688 74ACTQ841 Functional Description The ACTQ841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state. Logic Diagram Function Table Inputs OE LE H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Internal Output Function High Z High Z High Z Latched Transparent Latched Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACTQ841 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = − 0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = − 0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current Junction Temperature TJ PDIP − 0.5V to + 7.0V − 20 mA + 20 mA − 0.5V to VCC + 0.5V − 20 mA + 20 mA − 0.5V to VCC + 0.5V ± 50 mA ± 50 mA − 65°C to + 150°C ± 300 mA 140°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC − 40°C to + 85°C 125 mV/ns Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications.

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74ACTQ841 Quiet 10-Bit Transparent Latch with 3-STATE Outputs
74ACTQ841

Quiet 10-Bit Transparent Latch with 3-STATE Outputs

The ACTQ841 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 841 is a 10-bit transparent latch, a 10-bit version of the ACTQ841 utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance.
s Guaranteed simultaneous switching noise level and dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors s Improved latch-up immunity s Outputs source/sink 24 mA s Has TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACTQ841SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACTQ841SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

Pin Descriptions

Pin Names OE LE

Description Data Inputs 3-STATE Outputs Output Enable Latch Enable

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS010688
74ACTQ841

Functional Description

The ACTQ841 consists of ten D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state.

Logic Diagram

Function Table

Inputs

OE LE

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change

Internal Output

Function

High Z High Z High Z Latched Transparent Latched

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACTQ841

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = − 0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = − 0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source
or Sink Current

Junction Temperature TJ PDIP
− 0.5V to + 7.0V
− 20 mA + 20 mA − 0.5V to VCC + 0.5V
− 20 mA + 20 mA − 0.5V to VCC + 0.5V
± 50 mA
± 50 mA − 65°C to + 150°C
± 300 mA
140°C

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN from 0.8V to 2.0V VCC 4.5V, 5.5V
4.5V to 5.5V
0V to VCC 0V to VCC − 40°C to + 85°C 125 mV/ns

Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications.

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Datasheet ID: 74ACTQ841SPC 513222