74ACTQ563PC

74ACTQ563PC Datasheet

74ACTQ563 Quiet Series Octal Latch with 3-STATE Outputs

Part	Datasheet
74ACTQ563PC	74ACTQ563PC (pdf)

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74ACTQ563 Quiet Series Octal Latch with 3-STATE Outputs 74ACTQ563 Quiet Series Octal Latch with 3-STATE Outputs The ACTQ563 is a high speed octal latch with buffered common Latch Enable LE and buffered common Output Enable OE inputs. The ACTQ563 is functionally identical to the ACTQ573, but with inverted outputs. The ACTQ563 utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance. s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Inputs and outputs on opposite sides of package allow easy interface with microprocessors s Outputs source/sink 24 mA s Faster prop delays than standard ACT563 s Functionally identical to the ACTQ573 but with inverted outputs Ordering Code: Order Number Package Number Package Description 74ACTQ563PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Assignment for DIP IEEE/IEC Pin Descriptions Pin Names LE OE Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010631.prf 74ACTQ563 Functional Description The ACTQ563 contains eight D-type latches with 3-STATE complementary outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on Function Table the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but that does not interfere with entering new data into the latches. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Inputs OE LE D HXX HH L HHH HLX LHL L HH LLX Internal Q X H L NC H L NC Outputs Function High-Z High-Z High-Z Latched Transparent Transparent NC Latched Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACTQ563 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source or Sink Current −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65°C to +150°C

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74ACTQ563 Quiet Series Octal Latch with 3-STATE Outputs
74ACTQ563 Quiet Series Octal Latch with 3-STATE Outputs

The ACTQ563 is a high speed octal latch with buffered common Latch Enable LE and buffered common Output Enable OE inputs. The ACTQ563 is functionally identical to the ACTQ573, but with inverted outputs. The ACTQ563 utilizes Fairchild FACT Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO output control and undershoot corrector in addition to a split ground bus for superior performance.
s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors s Outputs source/sink 24 mA s Faster prop delays than standard ACT563 s Functionally identical to the ACTQ573 but with inverted
outputs
Ordering Code:

Order Number Package Number

Package Description
74ACTQ563PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

Pin Assignment for DIP

IEEE/IEC

Pin Descriptions

Pin Names LE OE

Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs

FACT , Quiet Series , FACT Quiet Series and GTO are trademarks of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010631.prf
74ACTQ563

Functional Description

The ACTQ563 contains eight D-type latches with 3-STATE complementary outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on

Function Table
the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but that does not interfere with entering new data into the latches.

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change

Logic Diagram

Inputs OE LE D HXX HH L HHH HLX LHL L HH LLX

Internal Q X H L NC H L NC

Outputs

Function

High-Z

High-Z

High-Z

Latched

Transparent

Transparent

NC Latched

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACTQ563

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source
or Sink Current
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
± 50 mA
± 50 mA −65°C to +150°C

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Datasheet ID: 74ACTQ563PC 513215